公开(公告)号：US20250060531A1

公开(公告)日：2025-02-20

申请号：US18938732

申请日：2024-11-06

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Xiaoqian Li ,  Tarek A. Ibrahim ,  Ravindranath Vithal Mahajan ,  Nitin A. Deshpande

IPC: G02B6/122 ,  G02B6/12

Abstract: Photonic packages and device assemblies that include photonic integrated circuits (PICs) coupled to optical lenses on lateral sides of the PICS. An example photonic package comprises a package support, an integrated circuit (IC), an insulating material, a PIC having an active side and a lateral side substantially perpendicular to the active side. At least one optical structure is on the active side. A substantial portion of the active side is in contact with the insulating material, and the PIC is electrically coupled to the package support and to the IC. The photonic package further includes an optical lens coupled to the PIC on the lateral side. In some embodiments, the photonic package further includes an interposer between the PIC or the IC and the package support.

公开(公告)号：US20250006678A1

公开(公告)日：2025-01-02

申请号：US18345437

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Harini Kilambi ,  Kimin Jun ,  Adel A. Elsherbini ,  John Edward Zeug Matthiesen ,  Trianggono Widodo ,  Adita Das ,  Mohit Bhatia ,  Dimitrios Antartis ,  Bhaskar Jyoti Krishnatreya ,  Rajesh Surapaneni ,  Xavier Francois Brun

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/544 ,  H01L25/065

Abstract: Disclosed herein are microelectronic assemblies, related apparatuses, and methods. In some embodiments, a microelectronic assembly may include a first die in a first layer; and a second and third die in a second layer, the second layer coupled to the first layer by hybrid bond interconnects having a first pad and a second pad, wherein the first pad is coupled to a first via in the second die and the first pad is offset from the first via by a first dimension, and the second pad is coupled to a second via in the third die and the second pad is offset from the second via by a second dimension different than the first dimension. In some embodiments, the first pad is offset from the first via in a first direction and the second pad is offset from the second via in a second direction different than the first direction.

公开(公告)号：US20250006653A1

公开(公告)日：2025-01-02

申请号：US18346108

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Bhaskar Jyoti Krishnatreya ,  Francisco Maya ,  Siyan Dong ,  Alveera Gill ,  Tan Nguyen ,  Keith E. Zawadzki

IPC: H01L23/544 ,  H01L23/00 ,  H01L25/065

Abstract: An apparatus comprising an integrated circuit device comprising a fiducial area of a first layer, the fiducial area comprising a metal area and a metal free area; and a plurality of zones that are metal free in multiple layers adjacent to the first layer, wherein the zones are defined by a footprint based on the fiducial area of the first layer and a second fiducial area of a second integrated circuit device, the footprint comprising multiple slits.

公开(公告)号：US11923307B2

公开(公告)日：2024-03-05

申请号：US16902958

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Bai Nie ,  Gang Duan ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Yikang Deng ,  Wei-Lun Jen ,  Tarek A. Ibrahim ,  Sri Ranga Sai Boyapati ,  Robert Alan May ,  Yosuke Kanaoka ,  Robin Shea McRee ,  Rahul N. Manepalli

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5381 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5386

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US11887962B2

公开(公告)日：2024-01-30

申请号：US16902927

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Mohit Bhatia ,  Sairam Agraharam ,  Edvin Cetegen ,  Anurag Tripathi ,  Malavarayan Sankarasubramanian ,  Jan Krajniak ,  Manish Dubey ,  Jinhe Liu ,  Wei Li ,  Jingyi Huang

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L24/30 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/17 ,  H01L2224/1703

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20230420409A1

公开(公告)日：2023-12-28

申请号：US17846086

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Omkar G. Karhade ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Nitin A. Deshpande ,  Pushkar Sharad Ranade ,  Wilfred Gomes ,  Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Joshua Fryman ,  Stephen Morein ,  Matthew Adiletta ,  Michael Crocker ,  Aaron Gorius

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L25/0652 ,  H01L24/08 ,  H01L23/5226 ,  H01L24/94 ,  H01L2224/80896 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L24/97

Abstract: Embodiments of an integrated circuit (IC) die comprise: a first region having a first surface and a second surface, the first surface being orthogonal to the second surface; and a second region attached to the first region along a planar interface that is orthogonal to the first surface and parallel to the second surface, the second region having a third surface coplanar with the first surface. The first region comprises: a dielectric material; layers of conductive traces in the dielectric material, each layer of the conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface; conductive vias through the dielectric material; and bond-pads on the first surface, the bond-pads comprising portions of the conductive traces exposed on the first surface, and the second region comprises a material different from the dielectric material.

公开(公告)号：US20230299049A1

公开(公告)日：2023-09-21

申请号：US17699028

申请日：2022-03-18

Applicant: Intel Corporation

Inventor： Nitin A. Deshpande ,  Omkar G. Karhade ,  Mohit Bhatia ,  Debendra Mallik

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/16 ,  H01L23/481 ,  H01L24/32 ,  H01L21/76898 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/3128 ,  H01L21/565 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2224/32225 ,  H01L2224/16145 ,  H01L2224/0401

Abstract: A microelectronic component and a method of forming same. The microelectronic component includes: a first substrate having first through vias therein, the first substrate including silicon or glass; a first layer on a front surface of the first substrate and including one or more first dies coupled to the first through vias; a second substrate on a front surface of first layer and having second through vias therein and including silicon or glass; a second layer on a front surface of the second substrate, the first layer between the first substrate and the second substrate, the second layer including one or more second dies coupled to the second through vias; and electrically conductive structures on a back surface of the first substrate coupled to the first through vias.

公开(公告)号：US11735558B2

公开(公告)日：2023-08-22

申请号：US17740501

申请日：2022-05-10

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Mohit Bhatia ,  Anurag Tripathi ,  Takeshi Nakazawa ,  Steve Cho

IPC: H01L23/538 ,  H01L23/00

CPC classification number: H01L24/30 ,  H01L23/5384 ,  H01L24/17 ,  H01L2224/1703

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20230089494A1

公开(公告)日：2023-03-23

申请号：US17482311

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Xiaoqian Li ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Srinivas V. Pietambaram ,  Mitul Modi

IPC: G02B6/43 ,  G02B6/42

Abstract: Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include a PIC in a first layer having a first surface and an opposing second surface, wherein the first layer includes an insulating material, wherein the PIC has an active side, an opposing backside, and a lateral side substantially perpendicular to the active side and backside, and wherein the PIC is embedded in the insulating material with the active side facing up; an integrated circuit (IC) in a second layer at the second surface of the first layer, wherein the IC is electrically coupled to the active side of the PIC; and an optical component, having a reflector, optically coupled to the lateral side of the PIC and extending at least partially through the insulating material in the first layer along the lateral side of the PIC.

公开(公告)号：US20230081139A1

公开(公告)日：2023-03-16

申请号：US17475726

申请日：2021-09-15

Applicant: Intel Corporation

Inventor： Krishna Vasanth Valavala ,  Chandra Mohan Jha ,  Andrew Paul Collins ,  Omkar G. Karhade

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L23/367 ,  H01L25/00

Abstract: An example microelectronic assembly includes a substrate, a bridge die over the substrate, and a die stack between the substrate and the bridge die, the die stack including a logic die and at least one memory die, where the logic die is between the at least one memory die and the bridge die.