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公开(公告)号：US4722075A
公开(公告)日：1988-01-26
申请号：US786991
申请日：1985-10-15
摘要： An array of transistor memory cells of a type in which each cell has a transistor, a ground select switch and a sense amplifier coupling switch. A bias voltage line on which there is established a voltage V.sub.BIAS is coupled to each bit line by a bit line transistor whose gate during a read mode is at least about a voltage V.sub.T above V.sub.BIAS. Similarly, the source of each transistor is coupled to the bias voltage line by a source line transistor whose gate is more than about a voltage V.sub.T about V.sub.BIAS. The foregoing arrangement ensures that for every non-selected transistor that transistor's source voltage will be equal to its drain voltage so that all non-selected transistors will be substantially non-conducting.
摘要翻译： 一种晶体管存储单元的阵列，其中每个单元具有晶体管，接地选择开关和读出放大器耦合开关。 建立电压VBIAS的偏置电压线通过位线晶体管耦合到每个位线，位线晶体管在读取模式期间的栅极至少约为高于VBIAS的电压VT。 类似地，每个晶体管的源极通过其栅极大约约VBIAS的电压VT的源极线晶体管耦合到偏置电压线。 上述布置确保了对于每个未选择的晶体管，晶体管的源极电压将等于其漏极电压，使得所有未选择的晶体管将基本上不导通。
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公开(公告)号：US20130163713A1
公开(公告)日：2013-06-27
申请号：US13333850
申请日：2011-12-21
申请人： Eric Booth , Tyler Gomm , Kallol Mazumder , Scott E. Smith , John F. Schreck
发明人： Eric Booth , Tyler Gomm , Kallol Mazumder , Scott E. Smith , John F. Schreck
摘要： Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.
摘要翻译： 公开了用于双模禁止电路的电路，集成电路和方法。 在一个这样的示例性方法中，维持计数器，其中计数器指示在多个禁用周期中的至少一个的至少一部分期间输出信号将被禁用的逻辑电平。 由计数器指示的逻辑电平转换。 响应于指示输出信号被使能的使能信号，输出信号被提供作为输出信号，并且输出信号在由计数器指示的逻辑电平处被禁用，响应于使能信号，指示输出信号为 被禁用
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公开(公告)号：US08397129B2
公开(公告)日：2013-03-12
申请号：US13467699
申请日：2012-05-09
IPC分类号： H03M13/00
CPC分类号： G06F11/106 , G06F11/1056 , G06F11/1076
摘要： Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.
摘要翻译： 各种实施例包括用于扩展读取，修改和写入存储在存储器阵列中或正在提供给存储器阵列的数据的处理的装置，方法和系统，而不会中断要写入存储器阵列的连续的数据流。 实施例可以包括一种包括存储器阵列和错误代码模块的装置，该错误代码模块具有数据缓冲器，该数据缓冲器具有多个数据突发寄存器，该多个数据突发寄存器可操作以在相应的多个数据突发寄存器上接收要写入存储器阵列的多个数据突发 的连续时钟周期。 错误代码模块可操作以在不超过多个连续时钟周期的两个连续周期的周期的时间段内对多个数据脉冲串中的每一个执行读/修改/写入处理。
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公开(公告)号：US06690606B2
公开(公告)日：2004-02-10
申请号：US10102221
申请日：2002-03-19
IPC分类号： G11C700
摘要： An asynchronous address interface circuit and method for converting unrestricted randomly scheduled address transitions of memory address signals into scheduled address events from which initiation of a sequence of memory access events can be based. The address interface circuit initiates a delay sequence based on a address transition detection pulse. In the event a new address transition detection pulse is received prior to completion of the delay sequence, the delay sequence is reset and restarted based on the new address transition detection pulse. The sequence of memory access events is initiated in response to the completion of the delay sequence.
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公开(公告)号：US5140554A
公开(公告)日：1992-08-18
申请号：US574835
申请日：1990-08-30
申请人： John F. Schreck , Phat C. Truong , David Tatman
发明人： John F. Schreck , Phat C. Truong , David Tatman
CPC分类号： G11C29/027 , G11C17/18 , G11C29/02 , G11C29/50 , G11C29/50008 , G01R31/31702 , G11C16/04
摘要： A test circuit for determining whether or not fuse-links of an integrated circuit have been opened or closed properly by, for example, a laser device. The test circuit of this invention, in one embodiment, includes a variable impedance, such as a P-channel transistor, connected between a voltage source and an output terminal, the impedance having one value with a first input applied to the variable impedance control terminal and having a second, larger value in response to a second input applied to the variable impedance control terminal. At least one programmable fuse-link and a gate are connected in series between the output terminal and a source of reference potential. A means for providing control inputs to the variable impedance is connected between a test mode input signal and the control terminal of the variable impedance. The means for providing control inputs to the P-channel transistor may include a second, current-mirror-connected P-channel transistor.
摘要翻译： 用于确定集成电路的熔丝线是否已经由例如激光装置正确地打开或闭合的测试电路。 在一个实施例中，本发明的测试电路包括连接在电压源和输出端之间的可变阻抗，例如P沟道晶体管，该阻抗具有一个值，第一输入端施加到可变阻抗控制端 并且响应于施加到可变阻抗控制端子的第二输入而具有第二较大的值。 在输出端子和参考电位源之间串联连接至少一个可编程熔丝管和栅极。 用于向可变阻抗提供控制输入的装置连接在测试模式输入信号和可变阻抗的控制端之间。 用于向P沟道晶体管提供控制输入的装置可以包括第二电流镜连接的P沟道晶体管。
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46.发明授权Method and apparatus for verifying the state of a plurality of electrically programmable memory cells 失效用于验证电子可编程存储器单元的多样性状态的方法和装置
公开(公告)号：US5124945A
公开(公告)日：1992-06-23
申请号：US737830
申请日：1991-07-29
申请人： John F. Schreck
发明人： John F. Schreck
IPC分类号： G11C29/00 , G11C16/02 , G11C16/04 , G11C16/10 , G11C16/34 , G11C17/00 , G11C29/12 , G11C29/50
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/3454 , G11C29/50 , G11C16/04 , G11C2029/5004
摘要： Apparatus for verifying the state of a plurality of electrically programmable memory cells (30-70) includes first and second memory cells (36, 38) each having current paths with first and second ends. A memory cell state sense node (BL2) is coupled to the first ends. A first array source node (82) is coupled to a second end of the current path of the first cell (36). A second array source node (84) is coupled to a second end of the current path of the second cell (38). First circuitry (160-198) is provided for sensing a program verify state (DATA, WE). Decoded ground circuitry (150, 144, 142) couples a selected one of the first and second array source nodes (140) to a low voltage source (Vss) in response to the first circuitry sensing a program verify state (DATA, WE). Second circuitry (130, 138, 134) selectively isolates at least a nonselected one of the first and second array source nodes (82, 84) from the voltage bias source in response to the first circuitry (160-198 ) sensing a program verify state (DATA, WE).
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公开(公告)号：US5120999A
公开(公告)日：1992-06-09
申请号：US652755
申请日：1991-02-08
IPC分类号： H03K19/003
CPC分类号： H03K19/00361
摘要： Resistors are used as controlling devices to control the rate at which output buffer transistors are turned OFF and ON to control transient noise. In one form the output buffer circuit comprises a NOR circuit having a first input coupled to a data input and a second input to an enable input, a NAND circuit having a first input coupled to the data input and a second input coupled to an enable input, a first inverter transistor pair having gates coupled to the output of the NOR circuit and having source-drain paths in series coupled to a reference, a second inverter transistor pair having gates coupled to the output of the NAND circuit and having source-drain paths coupled in series to a supply, a resistor coupled between in series between the source-drain paths of the first transistor pair and the supply, a resistor coupled in series between the second transistor pair and the reference, and a third inverter transistor pair with each gate of the third transistor pair coupled to one of the outputs of the first and second inverter transistor pairs and with the output of the third transistor pair coupled to the output of the buffer circuit.
摘要翻译： 电阻器用作控制装置，用于控制输出缓冲晶体管截止和接通的速率，以控制瞬态噪声。 在一种形式中，输出缓冲电路包括NOR电路，其具有耦合到数据输入的第一输入和到使能输入的第二输入，具有耦合到数据输入的第一输入的NAND电路和耦合到使能输入的第二输入 ，具有耦合到所述NOR电路的输出并且具有串联耦合到参考的源极 - 漏极路径的栅极的第一反相器晶体管对，具有耦合到所述NAND电路的输出并具有源极 - 漏极路径的栅极的第二反相器晶体管对 串联耦合到电源，电阻器串联耦合在第一晶体管对的源极 - 漏极路径和电源之间，串联耦合在第二晶体管对和基准之间的电阻器，以及与第二晶体管对和第三晶体管对之间的第三反相器晶体管对 第三晶体管对的栅极耦合到第一和第二反相器晶体管对的输出之一以及耦合到缓冲器ci的输出的第三晶体管对的输出 rcuit
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公开(公告)号：US5023837A
公开(公告)日：1991-06-11
申请号：US402402
申请日：1989-09-05
申请人： John F. Schreck , Debra J. Dolby
发明人： John F. Schreck , Debra J. Dolby
CPC分类号： G11C7/18 , G11C16/0416 , G11C16/0491 , G11C5/025 , G11C8/00
摘要： The memory array circuit this invention provides connection of segmented bitlines to bitline decoding circuitry while, at the same time, providing connection of combined wordlines wordline decoding circuitry. The segmentation and decoding connections permit faster speed of operation with minimal or no area penalty. The area penalty is avoided by driving common wordlines in each of the segments, effectively increasing the wordline pitch at the wordline decoder, while at the same time decreasing the number of wordline decodes required. The segmentation also permits location of the decoder circuit away from the signal and routing decode outputs.
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公开(公告)号：US4820941A
公开(公告)日：1989-04-11
申请号：US150863
申请日：1988-02-01
申请人： Debra J. Dolby , John F. Schreck , Phat Truong
发明人： Debra J. Dolby , John F. Schreck , Phat Truong
摘要： A driver circuit for applying both read and program voltages to a wordline of an integrated-circuit memory-cell logic array. The driver circuit is comprised of a series driver transistor pair, of a driver enabling means for enabling and disenabling one of the transistors of the driver transistor pair, and of a latching means. The driver transistor used during read operation may be constructed with a relatively short source-drain channel, permitting faster access speed during read operation of the circuit.
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公开(公告)号：US4802121A
公开(公告)日：1989-01-31
申请号：US869471
申请日：1986-06-02
CPC分类号： G11C16/0491
摘要： A memory array having two separate sets of parallel bit lines, and a word line intersecting the sets of bit lines. The memory cells are floating-gate MOS transistors having gates coupled to associated ones of the word lines and source-to-drain paths connected between alternating ones of the sets of bit lines and ground lines.
摘要翻译： 具有两组分离的并行位线的存储器阵列和与位线组相交的字线。 存储器单元是浮栅MOS晶体管，其具有耦合到字线中的相关联的栅极和连接在位线组和接地线中的交替的位置之间的源极到漏极路径的栅极。
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