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    Multiple step anneal method and semiconductor formed by multiple step anneal
    41.
    发明授权
    Multiple step anneal method and semiconductor formed by multiple step anneal 有权
    多步退火方法和多步退火形成的半导体

    公开(公告)号：US09018089B2

    公开(公告)日：2015-04-28

    申请号：US13221698

    申请日：2011-08-30

    申请人： Eric G. Liniger ,  Griselda Bonilla ,  Pak Leung ,  Stephen A. Cohen ,  Stephen M. Gates ,  Thomas M. Shaw

    发明人： Eric G. Liniger ,  Griselda Bonilla ,  Pak Leung ,  Stephen A. Cohen ,  Stephen M. Gates ,  Thomas M. Shaw

    IPC分类号： H01L21/26 ,  H01L21/3105 ,  H01L21/66 ,  H01L21/768

    CPC分类号： H01L21/3105 ,  H01L21/76828 ,  H01L21/76829 ,  H01L22/14

    摘要： A method of annealing a semiconductor and a semiconductor. The method of annealing including heating the semiconductor to a first temperature for a first period of time sufficient to remove physically-adsorbed water from the semiconductor and heating the semiconductor to a second temperature, the second temperature being greater than the first temperature, for a period of time sufficient to remove chemically-adsorbed water from the semiconductor. A semiconductor device including a plurality of metal conductors, and a dielectric including regions separating the plurality of metal conductors, the regions including an upper interface and a lower bulk region, the upper interface having a density greater than a density of the lower bulk region.

    摘要翻译： 半导体和半导体退火的方法。 退火方法包括将半导体加热到第一温度第一时间段，足以从半导体去除物理吸附的水，并将半导体加热到第二温度，第二温度大于第一温度一段时间 足以从半导体去除化学吸附的水。 一种包括多个金属导体的半导体器件，以及包括分隔多个金属导体的区域的电介质，所述区域包括上界面和下体块区域，所述上界面的密度大于所述下体积区域的密度。

    INTEGRATED TIME DEPENDENT DIELECTRIC BREAKDOWN RELIABILITY TESTING
    42.
    发明申请
    INTEGRATED TIME DEPENDENT DIELECTRIC BREAKDOWN RELIABILITY TESTING 有权
    集成时间依赖电介质断开可靠性测试

    公开(公告)号：US20130345997A1

    公开(公告)日：2013-12-26

    申请号：US13530782

    申请日：2012-06-22

    申请人： JIFENG CHEN ,  Dirk Pfeiffer ,  Thomas M. Shaw ,  Peilin Song ,  Franco Stellari

    发明人： JIFENG CHEN ,  Dirk Pfeiffer ,  Thomas M. Shaw ,  Peilin Song ,  Franco Stellari

    IPC分类号： G01R31/12 ,  G06F19/00

    CPC分类号： G01R31/2855 ,  G01R31/281 ,  G01R31/2817 ,  G01R31/2858 ,  G01R31/2879 ,  G01R31/311

    摘要： Methods for reliability testing include applying a stress voltage to a device under test (DUT); measuring a leakage current across the DUT; triggering measurement of optical emissions from the DUT based on the timing of the measurement of the leakage current; and correlating measurements of the leakage current with measurements of the optical emissions to determine a time and location of a defect occurrence within the DUT by locating instances of increased noise in the leakage current that correspond in time with instances of increased optical emissions.

    摘要翻译： 可靠性测试方法包括对被测设备（DUT）施加应力电压; 测量穿过DUT的漏电流; 基于泄漏电流测量的定时，触发DUT测量光发射; 并且将泄漏电流的测量与光发射的测量值相关联，以通过将泄漏电流中增加的噪声的实例定位在与增加的光发射的情况相对应的时间内来确定DUT内的缺陷发生的时间和位置。

    Building metal pillars in a chip for structure support
    44.
    发明授权
    Building metal pillars in a chip for structure support 有权
    建筑金属支柱在一个芯片的结构支持

    公开(公告)号：US07456098B2

    公开(公告)日：2008-11-25

    申请号：US11403332

    申请日：2006-04-13

    申请人： Habib Hichri ,  Xiao H. Liu ,  Vincent J. McGahay ,  Conal E. Murray ,  Jawahar P. Nayak ,  Thomas M. Shaw

    发明人： Habib Hichri ,  Xiao H. Liu ,  Vincent J. McGahay ,  Conal E. Murray ,  Jawahar P. Nayak ,  Thomas M. Shaw

    IPC分类号： H01L21/4763

    CPC分类号： H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-tip during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.

    摘要翻译： 通过支柱堆叠，例如金属通孔柱，在IC芯片的不同和指定位置处提供，以在加工期间支撑芯片结构以及任何相关的加工应力，例如热和机械应力。 这些堆叠的通孔柱从条带的基底衬底连接并延伸到芯片的顶部氧化物盖。 堆叠的通孔柱的主要目的是将芯片结构保持在一起以适应任何径向变形，并且还可以在处理或可靠性测试期间缓解任何应力，热和/或机械构造尖端。 堆叠的通孔柱通常不电连接到任何有源线或通孔，但是在一些实施例中，堆叠的通孔柱可以提供在芯片中提供电连接的附加功能。

    Process for interfacial adhesion in laminate structures through patterned roughing of a surface
    47.
    发明授权
    Process for interfacial adhesion in laminate structures through patterned roughing of a surface 有权
    通过图案化粗糙化表面的层压结构中的界面粘合方法

    公开(公告)号：US07972965B2

    公开(公告)日：2011-07-05

    申请号：US11862706

    申请日：2007-09-27

    申请人： Edward C. Cooney, III ,  Vincent McGahay ,  Thomas M. Shaw ,  Anthony K. Stamper ,  Matthew E. Colburn

    发明人： Edward C. Cooney, III ,  Vincent McGahay ,  Thomas M. Shaw ,  Anthony K. Stamper ,  Matthew E. Colburn

    IPC分类号： H01L21/311

    CPC分类号： H01L21/76829 ,  H01L21/31144 ,  H01L21/76828 ,  H01L21/78

    摘要： The present invention relates to a process for improved interfacial adhesion of dielectrics using patterned roughing. Improved adhesion strength between layers and substrates can be achieved through increasing the roughness of the interface between the materials. Roughness may including any disturbance of an otherwise generally smooth surface, such as grooves, indents, holes, trenches, and/or the like. Roughing on the interface may be achieved by depositing a material on a surface of the substrate to act as a mask and then using an etching process to induce the roughness. The material, acting as a mask, allows etching to occur on a fine, or sub-miniature, scale below the Scale achieved with a conventional photo mask and lithography to achieve the required pattern roughing. Another material is then deposited on the roughened surface of the substrate, filling in the roughing and adhering to the substrate.

    摘要翻译： 本发明涉及使用图案化粗糙化改善电介质的界面粘附的方法。 可以通过增加材料之间的界面的粗糙度来实现层和基底之间的改善的粘附强度。 粗糙度可能包括任何干扰通常平滑的表面，如凹槽，凹痕，孔，沟槽等。 可以通过在衬底的表面上沉积材料作为掩模，然后使用蚀刻工艺来引起粗糙度来实现界面上的粗加工。 用作掩模的材料允许蚀刻在以常规光掩模和光刻实现的规模以下的精细或次微小尺度上发生，以实现所需的图案粗糙化。 然后将另一种材料沉积在基底的粗糙表面上，填充粗加工并粘附到基底上。

    LOW k POROUS SiCOH DIELECTRIC AND INTEGRATION WITH POST FILM FORMATION TREATMENT
    48.
    发明申请
    LOW k POROUS SiCOH DIELECTRIC AND INTEGRATION WITH POST FILM FORMATION TREATMENT 审中-公开
    低k多孔SiCOH电介质和后期成膜处理的整合

    公开(公告)号：US20090061237A1

    公开(公告)日：2009-03-05

    申请号：US11846182

    申请日：2007-08-28

    申请人： Stephen M. Gates ,  Alfred Grill ,  Son Nguyen ,  Satyanarayana V. Nitta ,  Thomas M. Shaw

    发明人： Stephen M. Gates ,  Alfred Grill ,  Son Nguyen ,  Satyanarayana V. Nitta ,  Thomas M. Shaw

    IPC分类号： B32B27/06 ,  C08G77/00 ,  C08G77/12

    CPC分类号： C23C16/30 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02359 ,  H01L21/3105

    摘要： A porous SiCOH (e.g., p-SiCOH) dielectric film in which the stress change caused by increased tetrahedral strain is minimized by post treatment in unsaturated Hydrocarbon ambient. The inventive p-SiCOH dielectric film has more —(CHx) and less Si—O—H and Si—H bondings as compared to prior art p-SiCOH dielectric films. Moreover, a stable pSiOCH dielectric film is provided in which the amount of Si—OH (silanol) and Si—H groups at least within the pores has been reduced by about 90% or less by the post treatment. Hence, the inventive p-SiCOH dielectric film has hydrophobicity improvement as compared with prior art p-SiCOH dielectric films. In the present invention, a p-SiCOH dielectric film is produced that is flexible since the pores of the inventive film include stabilized crosslinking —(CHx)— chains wherein x is 1,2 or 3 therein. The dielectric film is produced utilizing an annealing step subsequent deposition that includes a gaseous ambient that includes at least one C—C double bond and/or at least one C—C triple bond.

    摘要翻译： 通过在不饱和烃环境中后处理使多孔SiCOH（例如，p-SiCOH）介电膜在其中由增加的四面体应变引起的应力变化最小化。 与现有技术的p-SiCOH介电膜相比，本发明的p-SiCOH电介质膜具有更多的（（CH x））和更少的Si-O-H和Si-H键。 此外，提供稳定的pSiOCH电介质膜，其中至少在孔内的Si-OH（硅烷醇）和Si-H基团的量通过后处理减少约90％以下。 因此，与现有技术的p-SiCOH介电膜相比，本发明的p-SiCOH介电膜具有疏水性改善。 在本发明中，由于本发明薄膜的孔包括其中x为1,2或3的稳定的交联 - （CHx） - 链，因此制备柔性的p-SiCOH介电膜。 介电膜是利用包括至少一个C-C双键和/或至少一个C-C三键的气态环境的退火步骤进行的。