公开(公告)号：US09006739B2

公开(公告)日：2015-04-14

申请号：US13448775

申请日：2012-04-17

申请人： James V. Crain, Jr. ,  Mark C. H. Lamorey ,  Christopher D. Muzzy ,  Thomas M. Shaw ,  David B. Stone

发明人： James V. Crain, Jr. ,  Mark C. H. Lamorey ,  Christopher D. Muzzy ,  Thomas M. Shaw ,  David B. Stone

IPC分类号： H01L21/66 ,  H01L23/522 ,  H01L23/00

CPC分类号： H01L22/34 ,  G01R31/2601 ,  G01R31/2607 ,  H01L23/522 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/13111 ,  H01L2224/14131 ,  H01L2224/14515 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/14

摘要： A method of testing an integrated circuit (IC) chip and a related test structure are disclosed. A test structure includes a monitor chain proximate to at least one solder bump pad, the monitor chain including at least one metal via stack, each metal via stack extending from a lower metal layer in the IC chip to an upper metal layer in the IC chip, such that the monitor chain forms a continuous circuit proximate to the at least one solder bump pad, and where each metal via stack is positioned substantially under the solder bump. A method for testing to detect boundaries of safe effective modulus includes performing a stress test on an IC chip containing the test structure joined to a semiconductor package.

公开(公告)号：US20130270558A1

公开(公告)日：2013-10-17

申请号：US13448775

申请日：2012-04-17

申请人： James V. Crain, JR. ,  Mark C. H. Lamorey ,  Christopher D. Muzzy ,  Thomas M. Shaw ,  David B. Stone

发明人： James V. Crain, JR. ,  Mark C. H. Lamorey ,  Christopher D. Muzzy ,  Thomas M. Shaw ,  David B. Stone

IPC分类号： H01L23/498 ,  H01L21/66

CPC分类号： H01L22/34 ,  G01R31/2601 ,  G01R31/2607 ,  H01L23/522 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/13111 ,  H01L2224/14131 ,  H01L2224/14515 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/14

摘要： A method of testing an integrated circuit (IC) chip and a related test structure are disclosed. A test structure includes a monitor chain proximate to at least one solder bump pad, the monitor chain including at least one metal via stack, each metal via stack extending from a lower metal layer in the IC chip to an upper metal layer in the IC chip, such that the monitor chain forms a continuous circuit proximate to the at least one solder bump pad, and where each metal via stack is positioned substantially under the solder bump. A method for testing to detect boundaries of safe effective modulus includes performing a stress test on an IC chip containing the test structure joined to a semiconductor package.

公开(公告)号：US08927869B2

公开(公告)日：2015-01-06

申请号：US13444343

申请日：2012-04-11

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC分类号： H05K1/00

CPC分类号： H01L24/05 ,  H01B3/306 ,  H01B3/307 ,  H01L21/02118 ,  H01L21/76877 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/03462 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/48

摘要： Wire-bonded semiconductor structures using organic insulating material and methods of manufacture are disclosed. The method includes forming a metal wiring layer in an organic insulator layer. The method further includes forming a protective layer over the organic insulator layer. The method further includes forming a via in the organic insulator layer over the metal wiring layer. The method further includes depositing a metal layer in the via and on the protective layer. The method further includes patterning the metal layer with an etch chemistry that is damaging to the organic insulator layer.

摘要翻译： 公开了使用有机绝缘材料的引线键合半导体结构和制造方法。 该方法包括在有机绝缘体层中形成金属布线层。 该方法还包括在有机绝缘体层上形成保护层。 该方法还包括在金属布线层上的有机绝缘体层中形成通孔。 该方法还包括在通孔中和保护层上沉积金属层。 该方法还包括用对有机绝缘体层有害的蚀刻化学物图案化金属层。

公开(公告)号：US08766439B2

公开(公告)日：2014-07-01

申请号：US12634741

申请日：2009-12-10

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC分类号： H01L23/12

CPC分类号： H01L24/11 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13618 ,  H01L2224/1362 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/1601 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2224/13099 ,  H01L2924/00012

摘要： Disclosed is a chip and method of forming the chip with improved conductive pads that allow for flexible C4 connections with a chip carrier or with another integrated circuit chip. The pads have a three-dimensional geometric shape (e.g., a pyramid or cone shape) with a base adjacent to the surface of the chip, a vertex opposite the base and, optionally, mushroom-shaped cap atop the vertex. Each pad can include a single layer of conductive material or multiple layers of conductive material (e.g., a wetting layer stacked above a non-wetting layer). The pads can be left exposed to allow for subsequent connection to corresponding solder bumps on a chip carrier or a second chip. Alternatively, solder balls can be positioned on the conductive pads to allow for subsequent connection to corresponding solder-paste filled openings on a chip carrier or a second chip.

摘要翻译： 公开了一种用改进的导电焊盘形成芯片的芯片和方法，其允许与芯片载体或另一个集成电路芯片的柔性C4连接。 垫具有三维几何形状（例如，金字塔或锥形），其具有与芯片表面相邻的基部，与基部相对的顶点以及可选地在顶点顶部的蘑菇形帽。 每个焊盘可以包括单层导电材料或多层导电材料（例如，堆叠在非润湿层上方的润湿层）。 焊盘可以被暴露以允许随后连接到芯片载体或第二芯片上的相应焊料凸块。 或者，焊球可以定位在导电焊盘上，以允许随后连接到芯片载体或第二芯片上相应的焊膏填充的开口。

公开(公告)号：US08546253B1

公开(公告)日：2013-10-01

申请号：US13415902

申请日：2012-03-09

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L24/05 ,  H01L21/31144 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/02313 ,  H01L2224/0236 ,  H01L2224/02375 ,  H01L2224/034 ,  H01L2224/03622 ,  H01L2224/0381 ,  H01L2224/0391 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/13111 ,  H01L2224/14104 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012

摘要： The invention provides a semiconductor chip structure having at least one aluminum pad structure and a polyimide buffering layer under the aluminum pad structure, wherein the polyimide buffering layer is self-aligned to the aluminum pad structure, and a method of forming the same. The method includes forming a polyimide buffering layer on a substrate, forming an aluminum pad structure on the buffering layer, and, using the aluminum pad structure as a mask, etching the substrate to remove the polyimide buffering layer from the substrate everywhere except under the aluminum pad structure.

摘要翻译： 本发明提供一种半导体芯片结构，其具有在铝焊盘结构下方的至少一个铝焊盘结构和聚酰亚胺缓冲层，其中聚酰亚胺缓冲层与铝焊盘结构自对准，以及其形成方法。 该方法包括在基板上形成聚酰亚胺缓冲层，在缓冲层上形成铝焊盘结构，并且使用铝焊盘结构作为掩模，蚀刻基板以除去铝以外的其他处理的基板 垫结构。

公开(公告)号：US08508043B2

公开(公告)日：2013-08-13

申请号：US13298183

申请日：2011-11-16

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  David L. Questad ,  Wolfgang Sauter ,  Timothy D. Sullivan

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  David L. Questad ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC分类号： H01L31/00

CPC分类号： H01L23/3171 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02126 ,  H01L2224/02235 ,  H01L2224/0401 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05552 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06051 ,  H01L2224/061 ,  H01L2224/0612 ,  H01L2224/06131 ,  H01L2224/13007 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13111 ,  H01L2224/1312 ,  H01L2224/14051 ,  H01L2224/141 ,  H01L2224/16225 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2924/00 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/00012

摘要： A topographical feature is formed proximate to a conductive bond pad that is used to couple a solder bump to a semiconductor die. The topographical feature is separated from the conductive bond pad by a gap. In one embodiment, the topographical feature is formed at a location that is slightly beyond the perimeter of the solder bump, wherein an edge of the bump is aligned vertically to coincide with the gap separating the conductive bond pad from the topographical feature. The topographical feature provides thickness enhancement of a non-conductive layer disposed over the semiconductor die and the conductive bond pad and stress buffering.

摘要翻译： 形成靠近用于将焊料凸块耦合到半导体管芯的导电接合焊盘的形貌特征。 地形特征与导电接合垫隔开间隙。 在一个实施例中，形貌特征形成在稍微超出焊料凸块周边的位置处，其中凸块的边缘垂直对齐，以将导电接合焊盘与形貌特征分开。 形貌特征提供了设置在半导体管芯上的非导电层的厚度增强和导电接合焊盘和应力缓冲。

公开(公告)号：US08242012B2

公开(公告)日：2012-08-14

申请号：US12845065

申请日：2010-07-28

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC分类号： H01L21/44

CPC分类号： H01L21/76885 ,  H01L21/76852 ,  H01L23/3114 ,  H01L23/525 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05007 ,  H01L2224/05008 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05552

摘要： Disclosed are embodiments of a structure having a metal layer with top surface and sidewall passivation and a method of forming the structure. In one embodiment, a metal layer is electroplated onto a portion of a seed layer at the bottom of a trench. Then, the sidewalls of the metal layer are exposed and, for passivation, a second metal layer is electroplated onto the top surface and sidewalls of the metal layer. In another embodiment, a trench is formed in a dielectric layer. A seed layer is formed over the dielectric layer, lining the trench. A metal layer is electroplated onto the portion of the seed layer within the trench and a second metal layer is electroplated onto the top surface of the metal layer. Thus, in this case, passivation of the top surface and sidewalls of the metal layer is provided by the second metal layer and the dielectric layer, respectively.

摘要翻译： 公开了具有具有顶表面和侧壁钝化的金属层的结构的实施例以及形成该结构的方法。 在一个实施例中，金属层电镀在沟槽底部的种子层的一部分上。 然后，暴露金属层的侧壁，为了钝化，将第二金属层电镀在金属层的顶表面和侧壁上。 在另一个实施例中，在电介质层中形成沟槽。 在电介质层上形成种子层，衬在沟槽上。 将金属层电镀在沟槽内的种子层的部分上，并且将第二金属层电镀到金属层的顶表面上。 因此，在这种情况下，金属层的顶表面和侧壁的钝化分别由第二金属层和电介质层提供。

公开(公告)号：US08237279B2

公开(公告)日：2012-08-07

申请号：US12879602

申请日：2010-09-10

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC分类号： H01L23/48

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02126 ,  H01L2224/034 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/10126 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： In one embodiment, a collar structure includes a non-conductive layer that relieves stress around the perimeter of each of the solder balls that connect the semiconductor die to the semiconductor chip package substrate, and another non-conductive layer placed underneath to passivate the entire surface of the die.

摘要翻译： 在一个实施例中，套环结构包括非导电层，其将围绕将半导体管芯连接到半导体芯片封装衬底的每个焊球的周边释放应力，以及放置在其下方以钝化整个表面的另一非导电层 的死亡。

公开(公告)号：US20120104600A1

公开(公告)日：2012-05-03

申请号：US13344628

申请日：2012-01-06

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Jeffrey S. Zimmerman

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Jeffrey S. Zimmerman

IPC分类号： H01L23/485

CPC分类号： H01L24/05 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05093 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/10122 ,  H01L2224/10126 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2224/05552

摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a dielectric material formed between a design sensitive structure and a passivation layer. The design sensitive structure comprising a lower wiring layer electrically and mechanically connected to a higher wiring level by a via farm. A method and structure is also provided.

摘要翻译： 设计结构体现在用于设计，制造或测试设计的机器可读介质中。 该设计结构包括在设计敏感结构和钝化层之间形成的电介质材料。 该设计敏感结构包括通过通孔连接器电连接和机械地连接到更高布线层的下布线层。 还提供了一种方法和结构。

公开(公告)号：US08114767B2

公开(公告)日：2012-02-14

申请号：US12046616

申请日：2008-03-12

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Jeffrey S. Zimmerman

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Jeffrey S. Zimmerman

IPC分类号： H01L21/4763

CPC分类号： H01L24/05 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05093 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/10122 ,  H01L2224/10126 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2224/05552

摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a dielectric material formed between a design sensitive structure and a passivation layer. The design sensitive structure comprising a lower wiring layer electrically and mechanically connected to a higher wiring level by a via farm. A method and structure is also provided.

摘要翻译： 设计结构体现在用于设计，制造或测试设计的机器可读介质中。 该设计结构包括在设计敏感结构和钝化层之间形成的电介质材料。 该设计敏感结构包括通过通孔连接器电连接和机械地连接到更高布线层的下布线层。 还提供了一种方法和结构。