摘要:
The present invention relates to a circuit arrangement having the following features: a load transistor having a control connection and a first and second load connection; a drive connection coupled to the control connection of the load transistor and serving for the application of a drive signal; a voltage limiting circuit connected between one of the load connections and the drive connection of the transistor; and a deactivation circuit connected to the voltage limiting circuit and serving for the deactivation of the voltage limiting circuit in a manner dependent on a deactivation signal, which is dependent on a load current through the load transistor and/or on a drive voltage of the load transistor.
摘要:
An integrated circuit device includes a semiconductor chip and a control chip at different supply potentials. A lead chip island includes an electrically conductive partial region and an insulation layer. The semiconductor chip is arranged on the electrically conductive partial region of the lead chip island and the control chip is cohesively fixed on the insulation layer.
摘要:
A power circuit comprises a power transistor for feeding a load current to a load, a measuring transistor for coupling out a measurement current dependent on the load current, at least two coupling transistors for dividing the measurement current into an internal measurement current and into an external measurement current, wherein the external measurement current can be fed to an external evaluation circuit, and the internal measurement current is fed to an internal evaluation circuit for evaluation. A third coupling transistor can be coupled to the measuring transistor if a measuring device determines a non-coupled state, and the third coupling transistor can be decoupled from the measuring transistor if the measuring device determines a coupled state. The measuring device determines the coupled state if the external evaluation device is coupled to the power circuit, and the measuring device determines a non-coupled state if the external evaluation device is not coupled to the power circuit.
摘要:
An integrated circuit device includes a semiconductor chip and a control chip at different supply potentials. A lead chip island includes an electrically conductive partial region and an insulation layer. The semiconductor chip is arranged on the electrically conductive partial region of the lead chip island and the control chip is cohesively fixed on the insulation layer.
摘要:
Circuit arrangement having a power transistor and a drive circuit for the power transistorThe invention relates to a circuit arrangement having the following features: a power transistor (T) having a control terminal (G) and also a first and second load path terminal (D, S), the first load path terminal (D) of which is connected to a terminal for supply potential (V1) via an inductance-exhibiting line terminal (1) and the second load path terminal (S) of which serves for connecting a load (Z), and a first drive unit (10) for off-state driving of the power transistor (T) having an output (11) connected to the control terminal (G) of the power transistor (T1), and having a first current source arrangement (Iq1) connected between the output (AK) and a first drive potential (GND), in which case the first drive unit has a second current source arrangement (S2off, Iq2; S2off, Iq2, Iq21), which is connected to the output (AK) and which provides a current (I2; I2, I21) that is dependent on a temporal change in a terminal potential (Vd) at the first load path terminal (D) of the power transistor (T).
摘要翻译:具有功率晶体管和用于功率晶体管的驱动电路的电路装置技术领域本发明涉及具有以下特征的电路装置:具有控制端子(G)的功率晶体管(T)以及第一和第二负载路径端子(D ,S),其第一负载路径端子(D)经由电感显现线端子(1)连接到用于电源电位端子(V 1),并且其第二负载路径端子(S)用于连接 负载(Z)和用于断开状态驱动功率晶体管(T)的第一驱动单元(10),其具有连接到功率晶体管(T 1)的控制端子(G)的输出端(11),以及 具有连接在输出(AK)和第一驱动电位(GND)之间的第一电流源布置(Iq 1),在这种情况下,第一驱动单元具有第二电流源布置(S 2 off,Iq 2; S 2 off ,Iq 2,Iq 21),其连接到输出(AK)并且提供电流(I 2; I 2,I 21),其取决于功率晶体管(T)的第一负载路径端子(D)处的端子电位(Vd)的时间变化。
摘要:
A power semiconductor module (41) as H-bridge circuit (42) has four power semiconductor chips (N1, N2, P1, P2) and a semiconductor control chip (IC). The semiconductor chips (N1, N2, P1, P2, IC) are arranged on three mutually separate large-area lead chip contact areas (43 to 45) of a lead plane (80). The semiconductor control chip (IC) is arranged on a centrally arranged lead chip contact area (45). An n-channel power semiconductor chip (N1, N2) as low-side switch (58, 59) and a p-channel power semiconductor chip (P1, P2) as high-side switch (48, 49) are in each case arranged on two laterally arranged lead chip contact areas (43, 44). The n-channel power semiconductor chips (N1, N2) are jointly at an earth potential (50) and the p-channel power semiconductor chips (P1, P2) are electrically connected to separate supply voltage sources (VS1, VS2).
摘要:
A semiconductor component arrangement includes a power transistor and a temperature measurement circuit. The power transistor includes a gate electrode, a source zone, a drain zone and a body zone. The body zone is arranged in a first semiconductor zone of a first conduction type. The temperature measuring circuit comprises a temperature-dependent resistor and an evaluation circuit coupled to the temperature-dependent resistor. The resistor is formed by a portion of said first semiconductor zone.
摘要:
A power switching device has a power switching transistor connected in series in a load circuit with an inductive load portion and a commutation circuit. The commutation circuit is connected in parallel with the gate-drain or base-collector path of the power transistor and has a first Zener diode, which determines the commutation clamping voltage for switching on the power switching transistor during commutation, and an oppositely biased normal diode that is connected in series with the first Zener diode. The commutation circuit further has control elements in order to reduce, during a short time, the commutation clamping voltage at the beginning of each commutation cycle or after an adjustable delay from the beginning of each commutation cycle.
摘要:
The present invention relates to a circuit arrangement having a load transistor (T1) and a current sensing transistor (T2) coupled to the load transistor (T1), wherein a switch arrangement (S) having at least one first switch (S1; S1a, S1b) is connected downstream of the current sensing transistor (T2) in order to connect the current sensing transistor (T2) to a first or second evaluation circuit (BL1, BL2) depending on a control signal.