Hybrid quantum computing network
    41.
    发明授权

    公开(公告)号:US11847533B2

    公开(公告)日:2023-12-19

    申请号:US17110382

    申请日:2020-12-03

    摘要: A distributed computing network includes a quantum computation network and a processor. The quantum computation network includes one or more quantum processor units (QPUs) interconnected one with the other using quantum interconnects including each a quantum link and quantum network interface cards (QNICs), where each QPU is further connected to, using the QNIC, a quantum memory. The processor is configured to receive a quantum computation task, and, using a network interface card (NIC) (i) allocate the quantum computation task to the computation network, by activating any of the quantum interconnects between the QPUs according to the quantum computation task, and (ii) solve the quantum computation task using the quantum computation network.

    Consolidating multiple electrical data signals into an optical data signal on a multi-chip module using ASIC for controlling a photonics transceiver

    公开(公告)号:US11791903B2

    公开(公告)日:2023-10-17

    申请号:US17608170

    申请日:2019-05-13

    IPC分类号: H04B10/524 G02F1/21 G02F1/225

    摘要: A multi-chip module (MCM-10) includes a substrate (11), one or more photonic chips (14) disposed on the substrate, and an electronic chip (12) disposed on the substrate. The one or more photonic chips include one or more optical channels (22), which are configured to guide propagating optical signals, and two or more photonic modulator-segments (18) coupled to each of the optical channels, each photonic modulator-segment configured to modulate the propagating optical signals responsively to digitally modulated driving electrical signals provided thereto. The electronic chip is configured to generate the digitally modulated driving electrical signals on multiple different lanes (16) of the electronic chip, synchronize the driving electrical signals on the multiple lanes to a same clock, separately control respective phases of the driving electrical signals, fine-tune the voltages of the driving electrical signals on the multiple lanes, and drive the photonic modulator-segments on the photonic chips with the synchronized and phase-controlled driving electrical signals.

    ACTIVE LEARNING OF PRODUCT INSPECTION ENGINE
    48.
    发明公开

    公开(公告)号:US20230237635A1

    公开(公告)日:2023-07-27

    申请号:US17584914

    申请日:2022-01-26

    摘要: A computing entity is described that obtains at least one inspection image of an at least partially fabricated product and causes the at least one inspection image to be processed by a product inspection engine. The product inspection engine includes a machine learning-trained model. The computing entity obtains an inspection result determined based on the processing of the at least one inspection image by the product inspection engine; identifies one or more training images stored in an image database based at least in part on the at least one inspection image; associates automatically generated labeling data with the one or more training images based at least in part on the inspection result determined by the processing of the at least one inspection image; and causes training of the product inspection engine using the one or more training images and the associated labeling data.

    PACKET SWITCHES
    49.
    发明公开
    PACKET SWITCHES 审中-公开

    公开(公告)号:US20230224262A1

    公开(公告)日:2023-07-13

    申请号:US17648260

    申请日:2022-01-18

    IPC分类号: H04L49/00 H04L49/101

    摘要: Switches for performing packet switching and associated methods are provided. An example switch includes an ingress port for receiving a packet. The switch includes a plurality of egress ports for discharging the packet from the switch. The switch includes a plurality of egress queues with each egress queue associated with one of the plurality of egress ports. The switch includes a control plane configured to determine a descriptor associated with a packet, determine a first egress port from which to discharge the at least one packet and to transmit the descriptor to an egress queue associated with the first egress port. The switch includes a descriptor crossbar configured to transmit the descriptor from the egress queue to a second egress port of the plurality of egress ports. The switch includes a packet crossbar configured to transmit the at least one packet from the ingress port to the second egress port.