公开(公告)号：US20200301590A1

公开(公告)日：2020-09-24

申请号：US16361864

申请日：2019-03-22

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell ,  Naveh Malihi

IPC: G06F3/06 ,  G11C7/06

Abstract: Apparatuses and methods related to updating data lines for data generation in, for example, a memory device or a computing system that includes a memory device. Updating data lines can include updating a plurality of data lines. The plurality of data lines can provide data form the memory array responsive to a receipt of the access command. The plurality of data lines can also be updated responsive to a determination that an access command received at a memory device is unauthorized.

公开(公告)号：US10762946B2

公开(公告)日：2020-09-01

申请号：US16237013

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

IPC: G11C11/406 ,  G11C11/4074 ,  G11C16/10 ,  G11C11/4072

Abstract: Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory system includes a memory controller and a memory device operably connected to the memory controller. The memory device includes (i) a memory array having a plurality of memory cells arranged in a plurality of memory regions and (ii) inhibit circuitry. In some embodiments, the inhibit circuitry is configured to disable one or more memory regions of the plurality of memory regions from receiving refresh commands such that memory cells of the one or more memory regions are not refreshed during refresh operations of the memory device. In these and other embodiments, the memory controller is configured to track memory regions that include utilized memory cells and/or to write data to the memory regions in accordance with a programming sequence of the memory device.

公开(公告)号：US10748600B2

公开(公告)日：2020-08-18

申请号：US16216894

申请日：2018-12-11

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  George B. Raad ,  Debra M. Bell ,  Markus H. Geiger ,  Anthony D. Veches

IPC: G11C11/4094 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/406

Abstract: Methods, systems, and devices for phase charge sharing are described. In some memory systems or memory devices, one or more decoders may be used to bias access lines of a memory die. The decoders may transfer voltage or current between a first conductive line of the decoder and a second conductive line of the decoder via a shorting device. Transferring the voltage or current may be performed as part of or in association with an operation (e.g., an activate or pre-charge operation) to access one or more memory cells of the memory die. In some examples, the decoders may transfer voltage or current between a first conductive line of a decoder associated with a first refresh activity and a second conductive line of the decoder associated with a second refresh activity via a shorting device.

公开(公告)号：US20190096894A1

公开(公告)日：2019-03-28

申请号：US16204409

申请日：2018-11-29

Applicant: Micron Technology Inc.

Inventor： Debra M. Bell ,  Scott J. Derner

IPC: H01L27/11 ,  H01L21/762 ,  G11C11/412 ,  G11C11/419

CPC classification number: H01L27/1112 ,  G11C11/412 ,  G11C11/419 ,  H01L21/76202 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/1104 ,  H01L27/1108

Abstract: Some embodiments include memory cells having four transistors supported by a base, and vertically offset from the base. The four transistors are incorporated into first and second inverters having first and second inverter outputs, respectively. A first access transistor gatedly couples the first inverter output to a first comparative bitline, and second access transistor gatedly couples the second inverter output to a second comparative bitline. The first and second access transistors have first and second gates coupled to one another through a wordline. The four transistors are along a first side of the wordline, and are vertically displaced from the wordline. The first and second comparative bitlines are laterally adjacent to one another along a second side of the wordline, and are vertically displaced from the wordline. Some embodiments include memory arrays.

公开(公告)号：US20180032458A1

公开(公告)日：2018-02-01

申请号：US15220177

申请日：2016-07-26

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell

IPC: G06F13/366 ,  G06F13/28 ,  G06F13/24

CPC classification number: G06F13/366 ,  G06F11/00 ,  G06F13/1668 ,  G06F13/24 ,  G06F13/287 ,  G11C7/00 ,  G11C7/24

Abstract: The present disclosure includes apparatuses and methods related to accessing status information. One example apparatus comprises a host and a memory device coupled to the host. The memory device includes a controller configured to provide, to a status arbiter, a status signal indicating whether a status register of the controller contains generated status information. Responsive to the status signal indicating that the status register contains the generated status information, the controller can also provide the status information from the controller to the status arbiter via a status intermediary.

公开(公告)号：US20180012636A1

公开(公告)日：2018-01-11

申请号：US15205885

申请日：2016-07-08

Applicant: Micron Technology, Inc.

Inventor： Joshua E. Alzheimer ,  Debra M. Bell

IPC: G11C7/06 ,  G11C7/22

CPC classification number: G11C7/06 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091

Abstract: Examples include apparatuses and methods related to scan chain operation in sensing circuitry. A number of embodiments include an apparatus comprising an array of memory cells coupled to sensing circuitry having a sense amplifier and a compute component, the sensing circuitry to receive a scan vector and perform a scan chain operation on the scan vector.

公开(公告)号：US09047978B2

公开(公告)日：2015-06-02

申请号：US14010120

申请日：2013-08-26

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell ,  Jeff A. McClain ,  Brian P. Callaway

IPC: G11C7/00 ,  G11C11/406 ,  G11C7/10

CPC classification number: G11C11/406 ,  G11C7/1012

Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.

Abstract translation: 本文公开了用于选择行刷新的装置和方法。 示例性装置可以包括刷新控制电路。 刷新控制电路可以被配置为从地址总线接收与目标多个存储器单元相关联的目标地址。 刷新控制电路还可以被配置为至少部分地响应于确定已经发生了多个刷新操作来向地址总线提供邻近地址。 在一些示例中，与邻近地址相关联的多个存储单元可以是与目标多个存储单元相邻的多个存储单元。

公开(公告)号：US20140119141A1

公开(公告)日：2014-05-01

申请号：US13660768

申请日：2012-10-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Robert Tamlyn ,  Debra M. Bell ,  Michael Roth ,  Eric A. Becker ,  Tyrel Z. Jensen

IPC: G11C8/18

CPC classification number: G11C29/028 ,  G11C7/1066 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/222 ,  G11C29/022 ,  G11C29/023 ,  G11C2207/105

Abstract: Apparatuses and methods for capturing data in a memory are disclosed herein. An apparatus may include a command path and a data capture logic. The command path may be configured to receive a command signal and to delay the command signal with a delay based, at least in part, on a plurality of propagation delays. The data capture logic may be coupled to the command path and configured to receive the delayed command signal and a data strobe signal. The data capture logic may further be configured to capture data according to the data strobe signal responsive, at least in part, to receipt of the delayed command signal.

Abstract translation: 本文公开了用于在存储器中捕获数据的装置和方法。 装置可以包括命令路径和数据捕获逻辑。 命令路径可以被配置为接收命令信号并且至少部分地基于多个传播延迟延迟基于延迟的命令信号。 数据捕获逻辑可以耦合到命令路径并且被配置为接收延迟的命令信号和数据选通信号。 数据采集​​逻辑还可以被配置为至少部分地响应于接收延迟的命令信号而根据数据选通信号捕获数据。

公开(公告)号：US20250103416A1

公开(公告)日：2025-03-27

申请号：US18909706

申请日：2024-10-08

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell ,  Kristen M. Hopper ,  Erika Prosser ,  Aaron P. Boehm

IPC: G06F11/07 ,  G06F1/20 ,  G06F1/30 ,  G06F3/06 ,  G06F11/30

Abstract: Methods, systems, and devices for persistent health monitoring for volatile memory devices are described. A memory device may determine that an operating condition associated with an array of memory cells on the device, such as a temperature, current, voltage, or other metric of health status is outside of a range associated with a risk of device degradation. The memory device may monitor a duration over which the operating condition is outside of the range, and may determine whether the duration satisfies a threshold. In some cases, the memory device may store an indication of when (e.g., each time) the duration satisfied the threshold. The memory device may store the one or more indications in one or more non-volatile storage elements, such as fuses, which may enable the memory device to maintain a persistent indication of a cumulative duration over which the memory device is operated with operating conditions outside of the range.

公开(公告)号：US20240078153A1

公开(公告)日：2024-03-07

申请号：US18313670

申请日：2023-05-08

Applicant: Micron Technology, Inc.

Inventor： Aaron Jannusch ,  Brett K. Dodds ,  Debra M. Bell ,  Joshua E. Alzheimer ,  Scott E. Smith

IPC: G06F11/10

CPC classification number: G06F11/1044 ,  G06F11/102 ,  G06F11/1032

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may access a group of memory cells (e.g., portion of an array configurable to store ECC parity bits) otherwise reserved for ECC functionality of a memory device. The memory device may include a register to indicate whether its ECC functionality is enabled or disabled. When the register indicates the ECC functionality is disabled, the memory device may increase a storage capacity available to the host device by making the group of memory cells available for user-accessible data. Additionally or alternatively, the memory device may store metadata associated with various operational aspects of the memory device in the group of memory cells. Moreover, the memory device may modify a burst length to accommodate additional information to be stored in or read from the group of memory cells.