公开(公告)号：US20180375502A1

公开(公告)日：2018-12-27

申请号：US16121237

申请日：2018-09-04

Applicant: Micron Technology, Inc.

Inventor： Dong Pan ,  John D. Porter

IPC: H03K5/007 ,  H03K5/156 ,  H03K17/16

Abstract: An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.

公开(公告)号：US20180294806A1

公开(公告)日：2018-10-11

申请号：US15482020

申请日：2017-04-07

Applicant: Micron Technology, Inc.

Inventor： Dong Pan ,  John D. Porter

IPC: H03K17/16 ,  H03K5/156 ,  H03K5/007

Abstract: An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.

公开(公告)号：US10097169B1

公开(公告)日：2018-10-09

申请号：US15482020

申请日：2017-04-07

Applicant: Micron Technology, Inc.

Inventor： Dong Pan ,  John D. Porter

IPC: H03K5/007 ,  H03K17/16 ,  H03K5/156

Abstract: An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.

公开(公告)号：US20140204689A1

公开(公告)日：2014-07-24

申请号：US14223647

申请日：2014-03-24

Applicant: Micron Technology, Inc.

Inventor： Gi-Hong Kim ,  John D. Porter

IPC: H03K17/16 ,  G11C11/419

CPC classification number: H03K17/162 ,  G11C7/1057 ,  G11C7/1096 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C11/419

Abstract: Apparatus and methods for driving a signal are disclosed. An example apparatus includes a pre-driver circuit and a driver circuit. The pre-driver circuit includes a step-down transistor and the driver circuit includes a pull-down transistor configured to be coupled to a reference voltage. In a first mode, the step-down transistor is configured to reduce a voltage provided to the pull-down transistor to less than a supply voltage, and in a second mode, the step-down transistor configured to provide the voltage of the supply voltage to the pull-down transistor. The pre-driver circuit of the example signal driver circuit may further include a step-up transistor configured to increase a voltage provided to a pull-up transistor of the driver circuit to greater than the reference voltage, and in the second mode, the step-up transistor configured to provide the voltage of the reference voltage to the pull-up transistor.

Abstract translation: 公开了用于驱动信号的装置和方法。 示例性设备包括预驱动器电路和驱动器电路。 预驱动器电路包括降压晶体管，并且驱动器电路包括被配置为耦合到参考电压的下拉晶体管。 在第一模式中，降压晶体管被配置为将提供给下拉晶体管的电压降低到小于电源电压，并且在第二模式中，降压晶体管被配置为提供电源电压 到下拉晶体管。 示例性信号驱动器电路的预驱动器电路还可以包括升压晶体管，其被配置为将提供给驱动器电路的上拉晶体管的电压增加到大于参考电压，并且在第二模式中，步骤 该晶体管被配置为向上拉晶体管提供参考电压的电压。

公开(公告)号：US20130141960A1

公开(公告)日：2013-06-06

申请号：US13752037

申请日：2013-01-28

Applicant: Micron Technology, Inc.

Inventor： Jennifer Taylor ,  John D. Porter

IPC: G11C13/00

CPC classification number: G11C13/0004 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/004 ,  G11C27/005 ,  G11C29/50 ,  G11C29/50008 ,  G11C2213/72 ,  G11C2213/79

Abstract: Methods and systems for measuring the resistance of multiple memory elements are disclosed. The memory elements may be multi-bit memory and through precise measurement of resistance of the multi-bit memory elements, determination of how many and which memory elements fall into specific memory ranges can be accomplished. Furthermore, storage and/or display of this information may allow for the creation of resistance distribution histograms for modeling of one or more memory arrays.

Abstract translation: 公开了用于测量多个存储元件的电阻的方法和系统。 存储器元件可以是多位存储器，并且通过精确测量多位存储器元件的电阻，可以实现多少和哪些存储器元件落入特定存储器范围的确定。 此外，该信息的存储和/或显示可以允许创建用于一个或多个存储器阵列的建模的电阻分布直方图。

公开(公告)号：US20240125851A1

公开(公告)日：2024-04-18

申请号：US18047386

申请日：2022-10-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenneth M. Curewitz ,  Jaime Cummins ,  John D. Porter ,  Bryce D. Cook ,  Jeffrey P. Wright

IPC: G01R31/319 ,  G01R31/3185

CPC classification number: G01R31/31907 ,  G01R31/318594 ,  G01R31/318597

Abstract: A memory controller and a physical interface layer may accommodate multiple memory types. In some examples, the memory controller and/or PHY may include a register that includes operating parameters for multiple operating modes. Different operating modes may be compatible with different memory types. In some examples, the memory controller and physical interface may be included in a system for testing multiple memory types. The system may provide multiple interfaces for communicating with the memory. The different communication types may be used for performing different tests and/or simulating different types of devices that may utilize the memory.

公开(公告)号：US20240071431A1

公开(公告)日：2024-02-29

申请号：US17899849

申请日：2022-08-31

Applicant: Micron Technology, Inc.

Inventor： Si Hong Kim ,  John D. Porter

IPC: G11C7/10 ,  G11C7/22 ,  G11C8/08

CPC classification number: G11C7/1039 ,  G11C7/1012 ,  G11C7/222 ,  G11C8/08

Abstract: Systems and method for sensing an accessed voltage value associated with a memory cell is described. In different embodiments, a memory array may include a different number of sense components. Moreover, each sense component may receive latching signals to latch the accessed voltage value of memory cells of the memory array based on different timings. For example, the memory array may latch digit line voltages of memory cells positioned farther from a respective word line driver at a later time based on a latching signal with a higher delay. Such memory arrays may include circuitry to receive and/or generate the delayed latching signals as well as selection circuitry for latching the digit line voltages based on a selected delayed latching signals.

公开(公告)号：US20240004751A1

公开(公告)日：2024-01-04

申请号：US18216254

申请日：2023-06-29

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  John D. Porter

IPC: G06F11/10

CPC classification number: G06F11/10

Abstract: An on-die controller can provide an error correction capability for data stored in an array of memory cells located on the same die as the on-die controller. The error correction capability provided by the on-die controller eliminates a need to transfer error correction code (ECC) data to an external controller that may have provided the error correction capability in lieu of the on-die controller, which can provide more channel bandwidth for other types of non-user data for further strengthening data reliability, security, integrity of the memory system.

公开(公告)号：US11804281B2

公开(公告)日：2023-10-31

申请号：US17450582

申请日：2021-10-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Donald M. Morgan ,  Alan J. Wilson ,  Bryan D. Kerstetter ,  John D. Porter

IPC: G06F11/00 ,  G11C29/00 ,  G06F11/16 ,  G06F11/18

CPC classification number: G11C29/70 ,  G06F11/16 ,  G06F11/1666 ,  G06F11/18

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for automatic soft post-package repair (ASPPR). A memory may receive a row address along with a signal indicating an ASPPR operation, such as a bad page flag being set. A word line engine generates a physical address based on the row address, and ASPPR registers stores the physical address. The time it takes from receiving the row address to storing the physical address may be within the timing of an access operation on the memory such as tRAS. The row address may specify a single page of information. If the bad page flag is set, then a subsequent PPR operation may blow fuses to encode the physical address stored in the ASPPR registers.

公开(公告)号：US11682447B2

公开(公告)日：2023-06-20

申请号：US17161204

申请日：2021-01-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dean D. Gans ,  John D. Porter

IPC: G06F3/06 ,  G11C11/40 ,  G11C11/4076 ,  G11C11/4074 ,  G06F13/16

CPC classification number: G11C11/4076 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/1689 ,  G11C11/4074

Abstract: Apparatuses and methods for input receiver circuits and receiver masks for electronic memory are disclosed. Embodiments of the disclosure include memory receiver masks having shapes other than rectangular shapes. For example, a receiver mask according to some embodiments of the disclosure may have a hexagonal shape. Other shapes of receiver masks may also be included in other embodiments of the disclosure. Circuits, timing, and operating parameters for achieving non-rectangular and various shapes of receiver mask are described.