公开(公告)号：US20150235691A1

公开(公告)日：2015-08-20

申请号：US14185194

申请日：2014-02-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jongtae Kwak

IPC: G11C11/4076

CPC classification number: G11C11/4076 ,  G11C7/222 ,  G11C2207/2272

Abstract: Apparatuses and methods for controlling timing circuit locking and/or latency during a change in clock frequency (e.g. gear down mode) are described herein. An example apparatus may include a timing circuit. The timing circuit may be configured to provide a clock signal to the forward path, adjust a rate of the clock signal responsive to receipt of a command to adjust the rate of the clock signal, select a feedback clock signal responsive to a loop delay of the timing circuit, and provide a control signal to an adjustable delay circuit of the forward path circuit. Another example apparatus may include a forward path configured to delay a signal based at least in part on a loop delay and a latency value, and a latency control circuit configured to provide an adjusted latency value as the latency value responsive to receipt of a command, wherein the forward path is configured to operate at least in part at an adjusted clock rate responsive to receipt of the command.

Abstract translation: 这里描述了用于在时钟频率变化（例如减速模式）期间控制定时电路锁定和/或等待时间的装置和方法。 示例性装置可以包括定时电路。 定时电路可以被配置为向正向路径提供时钟信号，响应于接收到调整时钟信号速率的命令来调整时钟信号的速率，响应于所述时钟信号的环路延迟选择反馈时钟信号 定时电路，并向前向路径电路的可调延迟电路提供控制信号。 另一个示例性装置可以包括被配置为至少部分地基于环路延迟和等待时间值来延迟信号的前向路径，以及延迟控制电路，被配置为响应于接收到命令而提供调整后的等待时间值作为等待时间值， 其中所述前向路径被配置为响应于所述命令的接收至少部分地以调整的时钟速率运行。

公开(公告)号：US20150091624A1

公开(公告)日：2015-04-02

申请号：US14566358

申请日：2014-12-10

Applicant: Micron Technology, Inc.

Inventor： Jongtae Kwak

IPC: H03L7/08 ,  H03L7/081

CPC classification number: H03L7/0802 ,  G11C7/1072 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/0818

Abstract: A clock generator having a delay locked loop and a delay control circuit. The delay locked loop receives an input clock signal and adjusts an adjustable delay circuit to generate an output clock signal that is synchronized with received input clock signal. The delay control circuit coupled to the delay locked loop generates a control signal to initialize the delay measure operation to adjust the adjustable delay circuit, after comparing the phase difference of the input clock signal and the output clock signal. The delay control circuit further generates a start measure control signal to start measuring a delay applied to the measurement signal propagating through the adjustable delay circuit, and generates a stop measure control signal to stop the delay measurement of the measurement signal. The delay adjustment of the delay locked loop is then adjusted to apply the delay measurement when synchronizing the input and output clock signals.

Abstract translation: 一种具有延迟锁定环路和延迟控制电路的时钟发生器。 延迟锁定环接收输入时钟信号并调整可调延迟电路以产生与接收的输入时钟信号同步的输出时钟信号。 耦合到延迟锁定环的延迟控制电路在比较输入时钟信号和输出时钟信号的相位差之后，产生控制信号以初始化延迟测量操作以调整可调延迟电路。 延迟控制电路还产生开始测量控制信号，以开始测量延迟通过可调延迟电路传播的测量信号的延迟，并产生停止测量控制信号以停止测量信号的延迟测量。 然后调整延迟锁定环路的延迟调整，以在同步输入和输出时钟信号时应用延迟测量。

公开(公告)号：US08928376B2

公开(公告)日：2015-01-06

申请号：US13736857

申请日：2013-01-08

Applicant: Micron Technology, Inc.

Inventor： Jongtae Kwak

IPC: H03L7/06 ,  H03L7/081 ,  G11C7/10 ,  H03L7/08 ,  G11C7/22

CPC classification number: H03L7/0802 ,  G11C7/1072 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/0818

Abstract: A clock generator having a delay locked loop and a delay control circuit. The delay locked loop receives an input clock signal and adjusts an adjustable delay circuit to generate an output clock signal that is synchronized with received input clock signal. The delay control circuit coupled to the delay locked loop generates a control signal to initialize the delay measure operation to adjust the adjustable delay circuit, after comparing the phase difference of the input clock signal and the output clock signal. The delay control circuit further generates a start measure control signal to start measuring a delay applied to the measurement signal propagating through the adjustable delay circuit, and generates a stop measure control signal to stop the delay measurement of the measurement signal. The delay adjustment of the delay locked loop is then adjusted to apply the delay measurement when synchronizing the input and output clock signals.

Abstract translation: 一种具有延迟锁定环路和延迟控制电路的时钟发生器。 延迟锁定环接收输入时钟信号并调整可调延迟电路以产生与接收的输入时钟信号同步的输出时钟信号。 耦合到延迟锁定环的延迟控制电路在比较输入时钟信号和输出时钟信号的相位差之后，产生控制信号以初始化延迟测量操作以调整可调延迟电路。 延迟控制电路还产生开始测量控制信号，以开始测量延迟通过可调延迟电路传播的测量信号的延迟，并产生停止测量控制信号以停止测量信号的延迟测量。 然后调整延迟锁定环路的延迟调整，以在同步输入和输出时钟信号时应用延迟测量。

公开(公告)号：US08878586B2

公开(公告)日：2014-11-04

申请号：US13863707

申请日：2013-04-16

Applicant: Micron Technology, Inc.

Inventor： Jongtae Kwak ,  Kang-Yong Kim

IPC: H03L7/06 ,  H03K5/14 ,  G11C7/22 ,  H03L7/00 ,  G11C7/10 ,  H03L7/081

CPC classification number: H03L7/00 ,  G11C7/1072 ,  G11C7/222 ,  H03L7/0814

Abstract: A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate clocks from the input reference clock and having a fixed phase difference therebetween. The coarse delay line may have a hierarchical or a non-hierarchical structure. A phase mixer receives these two intermediate clocks and generates the final output clock having a phase between the phases of the intermediate clocks. The coarse shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract translation: 时钟同步系统和方法避免了高频时的输出时钟抖动，并且在粗略和精细延迟的边界处实现了平滑的相位转变。 该系统可以使用单个粗延迟线，其被配置为从输入参考时钟产生两个中间时钟并且在它们之间具有固定的相位差。 粗延迟线可以具有分层结构或非分层结构。 相位混合器接收这两个中间时钟并产生具有在中间时钟的相位之间的相位的最终输出时钟。 在高时钟频率下延迟线中的粗略移位不影响馈送到相位混频器中的中间时钟之间的相位关系。 来自相位混频器的输出时钟与输入参考时钟同步，即使在高时钟频率输入时也不会出现任何抖动或噪音。 由于管理摘要的规则，本摘要不应用于解释索赔。

公开(公告)号：US20240371430A1

公开(公告)日：2024-11-07

申请号：US18653768

申请日：2024-05-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jongtae Kwak

IPC: G11C11/4076 ,  H03K3/037 ,  H03K19/20

Abstract: A semiconductor device may include a serializer circuit configured to generate an output clock signal for serialization. The serializer circuit may include a clock generator circuit configured to generate the output clock signal based on an input clock signal. Both the input and output clock signals may be multi-phase clock signals. The clock generator circuit may include an input clock buffer circuit, inverter circuits, a clock pulse circuit (e.g., a plurality of NAND gates in a configuration), and phase splitter circuits arranged in a configuration so as to reduce current leakage and allow for a smaller footprint, among other benefits. The clock generator circuit may provide the output clock signal to a serializer included in the serializer circuit for serialization.

公开(公告)号：US20240321332A1

公开(公告)日：2024-09-26

申请号：US18590760

申请日：2024-02-28

Applicant: Micron Technology, Inc.

Inventor： Jongtae Kwak

IPC: G11C8/18 ,  G11C7/22 ,  H03K19/20 ,  H03L7/081

CPC classification number: G11C8/18 ,  G11C7/222 ,  H03L7/0812 ,  H03K19/20

Abstract: Methods, systems, and devices for divided clock control are described. An even clock signal associated with transitioning edges of even-indexed pulses of a global clock signal and an odd clock signal associated with transitioning edges of odd-indexed pulses of a global clock signal may be received. An indication of whether a received command was received on a transitioning edge of an even-indexed pulse may be received. Based on the indication, whether to enable a propagation of the even clock signal to a first delay logic associated with even-indexed pulses or a second delay logic associated with odd-indexed pulses may be determined. Based on the determining, whether to delay a propagation of the command using the first delay logic and the even clock signal or the second delay logic and the odd clock signal may be determined.

公开(公告)号：US11799496B2

公开(公告)日：2023-10-24

申请号：US17726349

申请日：2022-04-21

Applicant: Micron Technology, Inc.

Inventor： Jongtae Kwak

IPC: G06F7/02 ,  H03M13/11 ,  G11C29/52 ,  G06F11/10

CPC classification number: H03M13/1108 ,  G06F11/1068 ,  G11C29/52

Abstract: Methods, systems, and devices for operating a memory device are described. An error correction bit flipping scheme may include methods, systems, and devices for performing error correction of one or more bits (e.g., a flip bit) and for efficiently communicating error correction information. The data bits and the flip bit (e.g., an error corrected flip bit) may be directly transmitted (e.g., to a flip decision component). The flip bit may be transmitted to the flip decision component over a dedicated and/or unidirectional line that is different from one or more other lines that carry data bits (e.g., to the flip decision component).

公开(公告)号：US11360848B2

公开(公告)日：2022-06-14

申请号：US16871329

申请日：2020-05-11

Applicant: Micron Technology, inc.

Inventor： Jongtae Kwak

IPC: G06F11/00 ,  G06F11/10 ,  G11C11/22 ,  G11C11/406 ,  G11C29/52 ,  G11C11/4076 ,  G11C11/4099 ,  G11C7/10 ,  G11C29/04

Abstract: Methods, systems, and devices for an error correcting code scrub scheme are described. A memory device may correct an error associated with a first data bit or a first parity bit of a plurality of data bits and a plurality of parity bits, respectively. The memory device may correct the error by reading each of the plurality of data bits and the plurality of parity bits from a memory array, and determining that an error associated with a single bit exists. The memory device may then correct the determined single-bit error, and may write the corrected bit directly back to the memory array.

公开(公告)号：US10795759B2

公开(公告)日：2020-10-06

申请号：US16126991

申请日：2018-09-10

Applicant: Micron Technology, Inc.

Inventor： Yoshiro Riho ,  Atsushi Shimizu ,  Sang-Kyun Park ,  Jongtae Kwak

IPC: G06F11/10 ,  G11C29/42 ,  G11C29/52 ,  H03M13/00 ,  G11C29/04 ,  G06F13/42

Abstract: Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories are described. An example apparatus includes an I/O circuit configured to receive first data and first ECC data associated with the first data, a memory array, and a control circuit. The control circuit is coupled between the I/O circuit and the memory array. The control circuit is configured to execute first ECC-decoding to produce corrected first data and corrected first ECC data responsive, at least in part, to the first data and the first ECC data. The control circuit is further configured to store both the corrected first data and the corrected first ECC data into the memory array.

公开(公告)号：US10658019B2

公开(公告)日：2020-05-19

申请号：US14636447

申请日：2015-03-03

Applicant: Micron Technology, Inc.

Inventor： Jongtae Kwak

IPC: G11C7/00 ,  G11C7/22 ,  G11C7/10 ,  H03L7/081 ,  H03K3/012 ,  H03K3/037 ,  H03L7/181

Abstract: A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of the input clock signal. The read latency control circuit captures a read command signal relative to the timing of the input clock signal and outputs the read command signal relative to the timing of the output clock signal such that the read command signal is outputted indicative of a specified read latency.