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    MEMORY SYSTEM DATA MANAGEMENT
    41.
    发明申请
    MEMORY SYSTEM DATA MANAGEMENT 审中-公开

    公开(公告)号：US20200089423A1

    公开(公告)日：2020-03-19

    申请号：US16691890

    申请日：2019-11-22

    Applicant: Micron Technology, Inc.

    Inventor： Ramin Ghodsi

    IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0802

    Abstract: The present disclosure includes apparatuses and methods for memory system data management. A number of embodiments include writing data from a host to a buffer in the memory system, receiving, at the buffer, a notification from a memory device in the memory system that the memory device is ready to receive data, sending at least a portion of the data from the buffer to the memory device, and writing the portion of the data to the memory device.

    DETERMINING DATA STATES OF MEMORY CELLS
    42.
    发明申请
    DETERMINING DATA STATES OF MEMORY CELLS 审中-公开

    公开(公告)号：US20190267102A1

    公开(公告)日：2019-08-29

    申请号：US16410406

    申请日：2019-05-13

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Tommaso Vali ,  Luca De Santis ,  Ramin Ghodsi

    IPC: G11C16/26 ,  G06F11/07 ,  G11C11/56 ,  G11C29/02

    Abstract: Methods of operating a memory include determining a voltage level of a plurality of voltage levels at which a memory cell is deemed to first activate in response to applying the to a control gate of that memory cell for each memory cell of a plurality of memory cells, determining a plurality of voltage level distributions from numbers of memory cells of a first subset of memory cells deemed to first activate at each voltage level of the plurality of voltage levels, determining a transition between a pair of voltage level distributions for each adjacent pair of voltage level distributions, and assigning a respective data state to each memory cell of a second subset of memory cells responsive to the determined voltage level at which that memory cell is deemed to first activate and respective voltage levels of the transitions for each adjacent pair of voltage level distributions.

    I/O BUFFER OFFSET MITIGATION
    43.
    发明申请
    I/O BUFFER OFFSET MITIGATION 审中-公开

    公开(公告)号：US20190214086A1

    公开(公告)日：2019-07-11

    申请号：US15864069

    申请日：2018-01-08

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Qiang Tang ,  Ramin Ghodsi

    IPC: G11C16/10 ,  G11C16/04 ,  H03K19/0185 ,  G11C16/26 ,  H03K19/00

    Abstract: Methods of operating an integrated circuit device, and integrated circuit devices configured to perform methods, including applying a particular voltage level to a first input of an input/output (I/O) buffer and to a second input of the I/O buffer, determining whether the I/O buffer is deemed to exhibit offset, and applying an adjustment to the I/O buffer offset while applying the particular voltage level to the first input of the I/O buffer and to the second input of the I/O buffer if the I/O buffer is deemed to exhibit offset.

    Apparatuses and methods for reducing read disturb
    45.
    发明授权
    Apparatuses and methods for reducing read disturb 有权

    公开(公告)号：US10134478B2

    公开(公告)日：2018-11-20

    申请号：US15436289

    申请日：2017-02-17

    Applicant: Micron Technology, Inc.

    Inventor： Feng Pan ,  Ramin Ghodsi ,  Qiang Tang

    IPC: G11C16/26 ,  G11C16/34 ,  G11C16/24 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16

    Abstract: Apparatuses and methods for reducing read disturb are described herein. An example apparatus may include a first memory subblock including a first select gate drain (SGD) switch and a first select gate source (SGS) switch, a second memory subblock including a second SGD switch and a second SGS switch, and an access line associated with the first and second memory subblocks. The apparatus may include a control unit configured to enable the first and second SGD switches and the first and second SGS switches during a first portion of a read operation and to provide a first voltage on the access line during the first portion. The control unit may be configured to disable the first SGD switch and the first SGS switches during a second portion of the read operation and to provide a second voltage on the access line during the second portion.

    Threshold voltage distribution determination
    48.
    发明授权
    Threshold voltage distribution determination 有权

    公开(公告)号：US09607692B2

    公开(公告)日：2017-03-28

    申请号：US14868604

    申请日：2015-09-29

    Applicant: Micron Technology, Inc.

    Inventor： Qiang Tang ,  Feng Pan ,  Ramin Ghodsi ,  Mark A. Helm

    IPC: G11C11/34 ,  G11C16/06 ,  G11C11/56 ,  G11C7/14 ,  G11C29/02 ,  G11C29/04

    CPC classification number: G11C11/5642 ,  G11C7/14 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

    Abstract: Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to determine a first current on a source line of an array of memory cells, the first current corresponding to a first quantity of memory cells of a group of memory cells that conducts in response to a first sensing voltage applied to an access line and determine a second current on the source line, the second current corresponding to a second quantity of memory cells of the group that conducts in response to a second sensing voltage applied to the access line. The number of apparatuses can include a controller configured to determine at least a portion of a Vt distribution corresponding to the group of memory cells based, at least in part, on the first current and the second current.

    Memory timing self-calibration
    49.
    发明授权
    Memory timing self-calibration 有权
    存储器定时自校准

    公开(公告)号：US09552856B2

    公开(公告)日：2017-01-24

    申请号：US15095347

    申请日：2016-04-11

    Applicant: Micron Technology, Inc.

    Inventor： Qiang Tang ,  Ramin Ghodsi

    IPC: G11C7/22 ,  G11C11/4076 ,  G11C7/10 ,  G11C16/32 ,  G11C29/02 ,  G11C16/10 ,  G11C11/4093 ,  G11C29/04

    CPC classification number: G11C7/22 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C16/10 ,  G11C16/32 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0409

    Abstract: Methods for memory input timing self-calibration, apparatuses for input timing self-calibration, and systems are disclosed. One such method includes sequentially programming a plurality of delay trim settings into a delay circuit of a data path. The data path can include a data latch coupled to the delay circuit. A clock is coupled to the data latch to clock data into the data latch. Transitions of the data are substantially aligned with transitions of the clock. An output of the data latch is read after each delay trim setting is programmed. A boundary is determined between a first output state of the data latch and a second output state of the data latch wherein the boundary is associated with a particular delay trim setting of the plurality of delay trim settings. The particular delay trim setting is programmed into the delay circuit.

    Abstract translation: 公开了用于存储器输入定时自校准的方法，用于输入定时自校准的装置和系统。 一种这样的方法包括将多个延迟微调设置顺序地编程到数据路径的延迟电路中。 数据路径可以包括耦合到延迟电路的数据锁存器。 时钟耦合到数据锁存器，将数据时钟数据插入数据锁存器。 数据的转换基本上与时钟的转换对齐。 在对每个延迟微调设置进行编程后，读取数据锁存器的输出。 在数据锁存器的第一输出状态和数据锁存器的第二输出状态之间确定边界，其中边界与多个延迟调整设置的特定延迟微调设置相关联。 特定的延迟调整设置被编程到延迟电路中。

    Data path with clock-data tracking
    50.
    发明授权
    Data path with clock-data tracking 有权
    数据路径与时钟数据跟踪

    公开(公告)号：US09460803B1

    公开(公告)日：2016-10-04

    申请号：US14864990

    申请日：2015-09-25

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Qiang Tang ,  Ali Feiz Zarrin Ghalam ,  Hoon Choi ,  Eric N. Lee ,  Ramin Ghodsi

    IPC: G11C16/26 ,  G11C7/22 ,  G11C16/32 ,  G11C7/10 ,  G11C16/04

    CPC classification number: G11C16/26 ,  G11C5/063 ,  G11C7/04 ,  G11C7/08 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/222 ,  G11C16/0483 ,  G11C16/32

    Abstract: A system includes a plurality of sensing devices, a first multiplexer, a plurality of local return clock signal paths, a second multiplexer, and a data latch. Each sensing device outputs data onto a respective local data path in response to a clock signal on a clock signal path. The first multiplexor passes data from a selected local data path to a global data path. Each local return clock signal path is coupled to the clock signal path at a respective sensing device such that each local return clock signal path is routed along with a respective local data path. The second multiplexor passes a return clock signal from a selected local return clock signal path corresponding to the selected local data path to a global return clock signal path. The data latch latches the data on the global data path into the data latch in response to the return clock signal on the global return clock signal path.

    Abstract translation: 系统包括多个感测装置，第一多路复用器，多个本地返回时钟信号路径，第二多路复用器和数据锁存器。 每个感测装置响应于时钟信号路径上的时钟信号将数据输出到相应的本地数据路径上。 第一多路复用器将数据从选定的本地数据路径传递到全局数据路径。 每个本地返回时钟信号路径在相应感测装置处耦合到时钟信号路径，使得每个本地返回时钟信号路径与相应的本地数据路径一起路由。 第二多路复用器将来自对应于所选择的本地数据路径的选择的本地返回时钟信号路径的返回时钟信号传递到全局返回时钟信号路径。 响应于全局返回时钟信号路径上的返回时钟信号，数据锁存器将全局数据通路上的数据锁存到数据锁存器中。

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