公开(公告)号：US11056178B1

公开(公告)日：2021-07-06

申请号：US16933829

申请日：2020-07-20

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Angelo Visconti

IPC: G11C7/06 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/404 ,  G11C11/4099 ,  G11C11/22 ,  G11C11/24

Abstract: Methods, systems, and devices for read operations based on a dynamic reference are described. A memory device may include a set of memory cells each associated with a capacitive circuit including a first and second capacitor. After receiving a read command, the memory device may couple each capacitive circuit with a respective memory cell (e.g., to transfer a charge stored by each respective memory cell to a capacitive circuit) and may couple the second capacitor of each capacitive circuit to a reference voltage bus. Thus, a reference voltage on the reference voltage bus may be based on an average charge across the second capacitors of each capacitive circuit. The memory device may then compare a charge stored by the first and second capacitors of each capacitive circuit with the reference voltage bus and may output a set of values stored by the set of memory cells based on the comparing.

公开(公告)号：US20210065763A1

公开(公告)日：2021-03-04

申请号：US16552984

申请日：2019-08-27

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Ferdinando Bedeschi ,  Riccardo Muzzetto

IPC: G11C11/22

Abstract: Methods, systems, and devices for word line timing management are described. In some examples, a digit line may be precharged as part of accessing a memory cell. The memory cell may include a storage component and a selection component. A word line may be coupled with the selection component, and the word line may be selected in order to couple the storage component with the digit line, by way of the selection component. The word line may be selected while the digit line is still being precharged, and the storage component may become coupled with the digit line with reduced delay after the end of precharging of the digit line, concurrent with the end of the precharging of the digit line, or while the digit line is still being charged. Related techniques for sensing a logic state stored by the memory cell are also described.

公开(公告)号：US20200051606A1

公开(公告)日：2020-02-13

申请号：US16544534

申请日：2019-08-19

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Ferdinando Bedeschi ,  Riccardo Muzzetto

IPC: G11C11/22

Abstract: Methods and devices for reading a memory cell using a sense amplifier with split capacitors is described. The sense amplifier may include a first capacitor and a second capacitor that may be configured to provide a larger capacitance during certain portions of a read operation and a lower capacitance during other portions of the read operation. In some cases, the first capacitor and the second capacitor are configured to be coupled in parallel between a signal node and a voltage source during a first portion of the read operation to provide a higher capacitance. The first capacitor may be decoupled from the second capacitor during a second portion of the read operation to provide a lower capacitance during the second portion.

公开(公告)号：US20200005868A1

公开(公告)日：2020-01-02

申请号：US16558683

申请日：2019-09-03

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C14/00 ,  G11C11/22

Abstract: The present disclosure includes apparatuses, methods, and systems for charge separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell, and determining a data state of the memory cell based, at least in part, on a comparison of an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell before a particular reference time and an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time.

公开(公告)号：US09576654B2

公开(公告)日：2017-02-21

申请号：US15152449

申请日：2016-05-11

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Riccardo Muzzetto

IPC: G11C7/00 ,  G11C13/00 ,  G11C7/12 ,  G11C8/08 ,  G11C7/14 ,  G11C7/06 ,  G11C29/02 ,  G11C29/04 ,  G11C29/12

CPC classification number: G11C13/004 ,  G11C7/062 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C29/025 ,  G11C29/028 ,  G11C2013/0052 ,  G11C2013/0054 ,  G11C2029/0409 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2207/063 ,  G11C2213/79

Abstract: Apparatuses, sense circuits, and methods for compensating for a voltage increase on a wordline in a memory is described. An example apparatus includes a bitline, a memory cell coupled to the bitline, a bipolar selector device coupled to the memory cell, a wordline coupled to the bipolar selector device, and a wordline driver coupled to the wordline. The apparatus further includes a model wordline circuit configured to model an impedance of the wordline and an impedance of the wordline driver, and a sense circuit coupled to the bitline and to the model wordline circuit. The sense circuit is configured to sense a state of the memory cell based on a cell current and provide a sense signal indicating a state of the memory cell. The sense circuit is further configured to adjust a bitline voltage responsive to an increase in wordline voltage as modeled by the model wordline circuit.

Abstract translation: 描述用于补偿存储器中的字线上的电压增加的装置，感测电路和方法。 示例性设备包括位线，耦合到位线的存储器单元，耦合到存储单元的双极选择器器件，耦合到双极选择器器件的字线和耦合到字线的字线驱动器。 该装置还包括：模型字线电路，被配置为模拟字线的阻抗和字线驱动器的阻抗，以及耦合到位线和模型字线电路的感测电路。 感测电路被配置为基于单元电流感测存储器单元的状态，并提供指示存储单元的状态的感测信号。 感测电路还被配置为响应于由模型字线电路建模的字线电压的增加来调整位线电压。

公开(公告)号：US09269431B2

公开(公告)日：2016-02-23

申请号：US14740074

申请日：2015-06-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Daniele Vimercati ,  Riccardo Muzzetto

IPC: G11C13/00 ,  G11C7/14 ,  G11C7/04 ,  G11C7/02

CPC classification number: G11C13/004 ,  G11C7/02 ,  G11C7/04 ,  G11C7/14 ,  G11C13/0004 ,  G11C2013/0045 ,  G11C2013/0054

Abstract: This disclosure relates to generating a reference current for a memory device. In one aspect, a non-volatile memory device, such as a phase change memory device, can determine a value of a data digit, such as a bit, stored in a non-volatile memory cell based at least partly on the reference current. The reference current can be generated by mirroring a current at a node that is biased by a voltage bias. A configurable resistance circuit can have a resistance that is configurable. The resistance of the configurable resistance circuit can be in series between the node and a resistive non-volatile memory element. In some embodiments, a plurality of non-volatile memory elements can each be electrically connected in series between the resistance of the configurable resistance circuit and a corresponding selector.

公开(公告)号：US09042190B2

公开(公告)日：2015-05-26

申请号：US13775868

申请日：2013-02-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Daniele Vimercati ,  Riccardo Muzzetto

IPC: G11C7/00 ,  G11C7/12 ,  G11C13/00 ,  G11C8/08 ,  G11C7/14 ,  G11C7/06 ,  G11C29/02 ,  G11C29/04 ,  G11C29/12

CPC classification number: G11C13/004 ,  G11C7/062 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C29/025 ,  G11C29/028 ,  G11C2013/0052 ,  G11C2013/0054 ,  G11C2029/0409 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2207/063 ,  G11C2213/79

Abstract: Apparatuses, sense circuits, and methods for compensating for a voltage increase on a wordline in a memory is described. An example apparatus includes a bitline, a memory cell coupled to the bitline, a bipolar selector device coupled to the memory cell, a wordline coupled to the bipolar selector device, and a wordline driver coupled to the wordline. The apparatus further includes a model wordline circuit configured to model an impedance of the wordline and an impedance of the wordline driver, and a sense circuit coupled to the bitline and to the model wordline circuit. The sense circuit is configured to sense a state of the memory cell based on a cell current and provide a sense signal indicating a state of the memory cell. The sense circuit is further configured to adjust a bitline voltage responsive to an increase in wordline voltage as modeled by the model wordline circuit.

Abstract translation: 描述用于补偿存储器中的字线上的电压增加的装置，感测电路和方法。 示例性设备包括位线，耦合到位线的存储器单元，耦合到存储单元的双极选择器器件，耦合到双极选择器器件的字线和耦合到字线的字线驱动器。 该装置还包括：模型字线电路，被配置为模拟字线的阻抗和字线驱动器的阻抗，以及耦合到位线和模型字线电路的感测电路。 感测电路被配置为基于单元电流感测存储器单元的状态，并提供指示存储单元的状态的感测信号。 感测电路还被配置为响应于由模型字线电路建模的字线电压的增加来调整位线电压。

公开(公告)号：US20250054543A1

公开(公告)日：2025-02-13

申请号：US18812133

申请日：2024-08-22

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto ,  Francesco Mastroianni ,  Ferdinando Bedeschi ,  Nevil N. Gajera

IPC: G11C13/00

Abstract: Methods, systems, and devices for memory cell read operation techniques are described. A memory device may determine a starting voltage for a second phase of a read operation for a set of memory cells which may have a different magnitude than a magnitude of a starting voltage of a first phase of the read operation. For example, the memory device may use an ending voltage of the first phase to determine the starting voltage for the second phase. In some cases, the starting voltage for the second phase may correspond to a difference of a voltage offset and the ending voltage of the first phase. As part of the second phase of the read operation, the memory device may apply a sequence of voltages to the set of memory cells in accordance with the determined starting voltage of the second phase.

公开(公告)号：US20240370186A1

公开(公告)日：2024-11-07

申请号：US18772553

申请日：2024-07-15

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Christophe Vincent Antoine Laurent ,  Riccardo Muzzetto

IPC: G06F3/06

Abstract: The present disclosure relates to providing multiple error correction code protection levels in memory. One device includes an array of memory cells and an operating circuit for managing operation of the array. The operating circuit comprises an encoding unit configured to generate a codeword for a first error correction code (ECC) protection level and a second ECC protection level, and decoding unit configured to perform an ECC operation on the codeword at the first ECC protection level and the second ECC protection level. The codeword comprises payload data stored in a plurality of memory cells of the array, and parity data associated with the payload data stored in parity cells of the array.

公开(公告)号：US12080350B2

公开(公告)日：2024-09-03

申请号：US17890912

申请日：2022-08-18

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Riccardo Muzzetto

IPC: G11C11/00 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/26

Abstract: The present disclosure includes apparatuses, methods, and systems for balancing data in memory. An embodiment includes a memory having a group of memory cells, wherein each respective memory cell is programmable to one of three possible data states, and circuitry to balance data programmed to the group between the three possible data states by determining whether the data programmed to the group is balanced for any one of the three possible data states, and upon determining the data programmed to the group is not balanced for any one of the three possible data states apply a rotational mapping algorithm to the data programmed to the group until the data is balanced for any one of the three possible data states and apply a Knuth algorithm to the data of the group programmed to the two of the three possible data states that were not balanced by the rotational mapping algorithm.