公开(公告)号：US20180301407A1

公开(公告)日：2018-10-18

申请号：US15486345

申请日：2017-04-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao Yeh ,  Min-Feng Hung ,  Chih-Wei Hu

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A three-dimensional (3D) semiconductor device is provided, comprising: a substrate having a first area and a second area, and the second area adjacent to and surrounding the first area (i.e. active area), wherein an array pattern is formed in the first area; a stack structure having multi-layers formed above the substrate, and the multi-layers comprising active layers (ex: conductive layers) alternating with insulating layers above the substrate. The stack structure comprises first sub-stacks related to the array pattern in the first area; and second sub-stacks separately disposed in the second area, and the second sub-stacks configured as first dummy islands surrounding the first sub-stacks of the array pattern.

公开(公告)号：US10014306B2

公开(公告)日：2018-07-03

申请号：US15290242

申请日：2016-10-11

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: H01L27/11519 ,  H01L27/1157 ,  H01L21/28 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/11578

CPC classification number: H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/40114 ,  H01L29/40117

Abstract: A memory structure and a manufacturing method for the same are disclosed. The memory structure comprises memory segments. Each of the memory segments comprises a memory array region, a memory selecting region adjacent to the memory array region, a semiconductor gate electrode, a semiconductor channel connecting to the semiconductor gate electrode, a gate dielectric layer, a gate electrode layer, and channel layer. The gate electrode layer and the semiconductor channel are in the memory selecting region. The gate electrode layer and the semiconductor channel are separated from each other by the gate dielectric layer. The channel layer and the semiconductor gate electrode are in the memory array region. The channel layer and the semiconductor gate electrode are separated from each other by the gate dielectric layer.

公开(公告)号：US09741569B2

公开(公告)日：2017-08-22

申请号：US14571540

申请日：2014-12-16

Applicant: Macronix International Co., Ltd.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: H01L21/22 ,  H01L21/38 ,  H01L21/225 ,  H01L27/11578

CPC classification number: H01L21/2256 ,  H01L21/2255 ,  H01L27/11578

Abstract: A method is provided for manufacturing a memory device. A strip of semiconductor material is formed having a memory region, a contact landing area region and a switch region between the memory region and the contact landing area region. A memory layer is formed on surfaces of the strip in the memory region. A plurality of memory cell gates is formed over the memory region of the strip. A switch gate is formed over the switch region of the strip. A doped insulating material is deposited over a portion of the strip between the contact landing area region and the memory region. Diffusion of dopant is caused from the doped insulating material into the strip in the portion of the strip.

公开(公告)号：US09679913B1

公开(公告)日：2017-06-13

申请号：US15343253

申请日：2016-11-04

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: A memory structure includes a 3D array of memory cells, a plurality of first conductive lines disposed on the 3D array, a plurality of second conductive lines disposed on the first conductive lines, a top metal plate disposed on the second conductive lines, and at least one strapping structure. The second conductive lines and the first conductive lines extend on different directions. The at least one strapping structure is configured for the first conductive lines and correspondingly disposed on at least one dummy region of the 3D array. Each strapping structure includes a connecting structure and a jumping line. The jumping line is disposed on and coupled to the connecting structure, and coupled to the top metal plate. The jumping line and the second conductive lines extend on the same direction.

公开(公告)号：US09412752B1

公开(公告)日：2016-08-09

申请号：US14861377

申请日：2015-09-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao Yeh ,  Chih-Wei Hu ,  Yu-Wei Jiang

IPC: H01L27/115 ,  H01L27/105

CPC classification number: H01L27/11565 ,  H01L21/28282 ,  H01L27/11582 ,  H01L29/42348

Abstract: A 3D NAND flash memory includes even and odd stacks of conductive strips. Some of the conductive strips in the stacks are configured as word lines. Data storage structures are disposed on the sidewalls of the even and odd stacks. Active pillars include even and odd semiconductor films on the data storage structures connected at the bottom ends so that the semiconductor films can be thin films having a U-shaped current path. An even pad connected to the even semiconductor film and an odd pad connected to the odd semiconductor film are disposed over the even and odd stacks respectively. A segment of a reference line is connected to the even pad, and an inter-level connector is connected to the odd pad. A segment of a bit line comprises an extension contacting the inter-level connector.

Abstract translation: 3D NAND闪速存储器包括偶数和奇数组的导电条。 堆叠中的一些导电条被配置为字线。 数据存储结构设置在偶数和奇数堆栈的侧壁上。 活性柱包括连接在底端的数据存储结构上的偶数和奇数半导体膜，使得半导体膜可以是具有U形电流通路的薄膜。 连接到偶数半导体膜的偶焊盘和连接到奇数半导体膜的奇数焊盘分别设置在偶数和奇数堆叠上。 参考线的段连接到偶数焊盘，并且级间连接器连接到奇数焊盘。 位线的段包括接触级间连接器的扩展。

公开(公告)号：US09236346B2

公开(公告)日：2016-01-12

申请号：US14617420

申请日：2015-02-09

Applicant: Macronix International Co., Ltd.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: H01L23/535 ,  H01L21/768 ,  H01L27/115 ,  H01L23/522 ,  H01L29/417 ,  H01L29/788 ,  H01L23/485

CPC classification number: H01L23/535 ,  H01L21/768 ,  H01L21/76838 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/522 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/41766 ,  H01L29/788 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device includes a substrate with a recess, having a bottom and sides, extending into the substrate from the substrate's upper surface. The sides include first and second sides oriented transversely to one another. A stack of alternating active and insulating layers overlie the substrate's surface and the recess. At least some of the active layers have an upper and lower portions extending along upper and lower planes over and generally parallel to the upper surface and to the bottom, respectively. The active layers have first and second upward extensions positioned along the first and second sides to extend from the lower portions of their respective active layers. Conductive strips adjoin the second upward extensions of the said active layers. The conductive strips can comprise sidewall spacers on the sides of the second upward extensions, the conductive strips connected to overlying conductors by interlayer conductors.

公开(公告)号：US09224750B1

公开(公告)日：2015-12-29

申请号：US14296173

申请日：2014-06-04

Applicant: Macronix International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Chih-Wei Hu ,  Yen-Hao Shih

IPC: H01L27/10 ,  H01L27/115 ,  H01L29/40

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28282 ,  H01L27/11565 ,  H01L29/511 ,  H01L29/518

Abstract: A memory array includes a plurality of ridge-shaped multi-layer stacks extending along a first direction, and a hard mask layer formed on top of the plurality of ridge-shaped multi-layer stacks. The hard mask layer includes a plurality of stripes vertically aligned with the plurality of ridge-shaped multi-layer stacks, respectively, a plurality of bridges connecting adjacent ones of the stripes along a second direction orthogonal to the first direction, and a plurality of hard mask through holes between the plurality of bridges and the plurality of stripes.

Abstract translation: 存储器阵列包括沿着第一方向延伸的多个脊形多层堆叠，以及形成在所述多个脊形多层堆叠的顶部上的硬掩模层。 硬掩模层分别包括与多个脊形多层堆叠垂直对准的多个条带，沿着与第一方向正交的第二方向连接相邻条纹的多个桥，以及多个硬 通过多个桥和多个条之间的孔掩模。

公开(公告)号：US12254949B2

公开(公告)日：2025-03-18

申请号：US18314153

申请日：2023-05-09

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Chih-Wei Hu

IPC: G11C7/00 ,  G11C5/06 ,  G11C7/06 ,  G11C16/08 ,  H01L23/00 ,  H01L25/065 ,  H10B41/20 ,  H10B41/40 ,  H10B43/20 ,  H10B43/40 ,  H10B80/00

Abstract: A memory device, such as a three-dimensional AND or NOR flash memory, includes a first chip and a second chip. The first chip has multiple source line switches, multiple bit line switches, multiple page buffers, and multiple sensing amplifiers. The first chip has multiple first pads. The second chip has multiple memory cells to form multiple memory cell blocks. Multiple second pads are on a first surface of the second chip to be respectively coupled to multiple local bit lines and multiple local source lines of the memory cell blocks. Each of the first pads is coupled to the corresponding second pads.

公开(公告)号：US20240121954A1

公开(公告)日：2024-04-11

申请号：US17963202

申请日：2022-10-11

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: H01L27/11582 ,  G11C16/04 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  G11C16/0466 ,  H01L27/1157

Abstract: A memory device includes a first stack structure including first gate layers and first insulating layers alternately stacked with each other. A first channel pillar extends through the first stack structure. A second stack structure is located on the first stack structure and includes second gate layers and second insulating layers alternately stacked with each other. A second channel pillar extends through the second stack structure and is separated from the first channel pillar. A first conductive pillar and a second conductive pillar are located in and electrically connecting with the first channel pillar and the second channel pillar. A charge storage structure is located between the first gate layers and the first channel pillar, and between the second gate layers and the second channel pillar. The memory device may be applied to a 3D AND flash memory.

公开(公告)号：US11825654B2

公开(公告)日：2023-11-21

申请号：US17113190

申请日：2020-12-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: H10B43/27 ,  H01L21/768 ,  G11C16/08

CPC classification number: H10B43/27 ,  G11C16/08 ,  H01L21/76885

Abstract: A memory device includes a stacked structure and at least one first element structure. The stacked structure is in a memory array region and a staircase contact region. The stacked structure includes first conductive layers and a second conductive layer arranged in a longitudinal direction. The memory array region and the staircase contact region are arranged in a first lateral direction. The at least one first element structure passes through the first conductive layers and the second conductive layer along the longitudinal direction. The first conductive layers surround a sidewall surface of the at least one first element structure. The second conductive layer includes conductive portions arranged in a second lateral direction. The conductive portions are completely separated from each other by the at least one first element structure. The first lateral direction is different from the second lateral direction.