公开(公告)号：US20220238151A1

公开(公告)日：2022-07-28

申请号：US17344555

申请日：2021-06-10

Applicant: MACRONIX International Co., Ltd.

Inventor： Yu-Hsuan Lin ,  Po-Hao Tseng ,  Feng-Min Lee ,  Ming-Hsiu Lee

IPC: G11C11/4093 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/408 ,  G06F7/501 ,  G06F7/523

Abstract: An in-memory computation device and computation method are provided. The in-memory computation device, including a memory cell array, an input buffer, and a sense amplifier, is provided. The memory cell array includes a memory cell block. The memory cell block corresponds to at least one word line, and stores multiple weight values. Memory cells on the memory cell block respectively store multiple bits of each weight value. The input buffer is coupled to multiple bit lines, and respectively transmits multiple input signals to the bit lines. The memory cell array performs a multiply-add operation on the input signals and the weight values to generate multiple first operation results corresponding to multiple bit orders. The sense amplifier adds the first operation results to generate a second operation result according to the bit orders corresponding to the first operation results.

公开(公告)号：US10763306B2

公开(公告)日：2020-09-01

申请号：US16515180

申请日：2019-07-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao Tseng ,  Dai-Ying Lee ,  Erh-Kun Lai

IPC: H01L27/24 ,  H01L45/00 ,  H01L29/417

Abstract: A resistive memory includes a semiconductor substrate, a dielectric layer, an insulating layer and a metal electrode layer. The semiconductor substrate has a top surface and a recess extending downwards into the semiconductor substrate from the top surface. The dielectric layer is disposed on the semiconductor substrate and has a first through-hole aligning the recess. The insulating layer is disposed in the first through-hole and the recess. The metal electrode layer is disposed on the insulating layer by which the metal electrode layer is isolated from the semiconductor substrate.

公开(公告)号：US10476002B2

公开(公告)日：2019-11-12

申请号：US15690353

申请日：2017-08-30

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu Lin ,  Feng-Min Lee ,  Po-Hao Tseng ,  Kai-Chieh Hsu

IPC: H01L45/00 ,  G11C13/00 ,  H05K3/34

Abstract: A method for treating a semiconductor structure comprising memory devices is provided, wherein a forming process is conducted to initialize operation of the memory devices. The semiconductor structure is subjected to a forming thermal treatment, and step of saving data to the memory devices is performed after the forming thermal treatment.

公开(公告)号：US20190341426A1

公开(公告)日：2019-11-07

申请号：US16515180

申请日：2019-07-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao Tseng ,  Dai-Ying Lee ,  Erh-Kun Lai

IPC: H01L27/24 ,  H01L45/00

Abstract: A resistive memory includes a semiconductor substrate, a dielectric layer, an insulating layer and a metal electrode layer. The semiconductor substrate has a top surface and a recess extending downwards into the semiconductor substrate from the top surface. The dielectric layer is disposed on the semiconductor substrate and has a first through-hole aligning the recess. The insulating layer is disposed in the first through-hole and the recess. The metal electrode layer is disposed on the insulating layer by which the metal electrode layer is isolated from the semiconductor substrate.

公开(公告)号：US10388698B2

公开(公告)日：2019-08-20

申请号：US15291203

申请日：2016-10-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao Tseng ,  Dai-Ying Lee ,  Erh-Kun Lai

IPC: H01L27/24 ,  H01L45/00

Abstract: A resistive memory includes a semiconductor substrate, a dielectric layer, an insulating layer and a metal electrode layer. The semiconductor substrate has a top surface and a recess extending downwards into the semiconductor substrate from the top surface. The dielectric layer is disposed on the semiconductor substrate and has a first through-hole aligning the recess. The insulating layer is disposed in the first through-hole and the recess. The metal electrode layer is disposed on the insulating layer by which the metal electrode layer is isolated from the semiconductor substrate.

公开(公告)号：US09852791B1

公开(公告)日：2017-12-26

申请号：US15487458

申请日：2017-04-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao Tseng ,  Ming-Hsiu Lee ,  Kai-Chieh Hsu ,  Yu-Yu Lin ,  Feng-Min Lee

IPC: G11C13/00 ,  H01L45/00 ,  H01L21/02 ,  H01L29/18

CPC classification number: G11C13/0059 ,  G06F21/70 ,  G06F21/73 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/023 ,  G11C29/028 ,  G11C2013/0083 ,  G11C2013/0092 ,  H01L21/02 ,  H01L29/18 ,  H01L45/00 ,  H01L45/06 ,  H04L9/0866 ,  H04L9/3278

Abstract: A semiconductor memory device includes programmable resistance memory cells and a controller which applies a forming pulse to first and second groups of the programmable resistance memory cells for inducing a change in the first group from an initial resistance range to an intermediate resistance range, and for inducing the second group having a resistance outside the intermediate range. When a forming rate is lower than a first forming threshold rate, the controller adjusts the forming pulse until the forming rate is higher than the first forming threshold rate. When a forming rate is higher than the first forming threshold rate but lower than a second forming threshold rate, the controller adjusts the forming pulse until the forming rate is higher than the second forming threshold rate. The controller applies a programming pulse to the first and second groups and generates a chip ID of the semiconductor memory device.

公开(公告)号：US20250086443A1

公开(公告)日：2025-03-13

申请号：US18464718

申请日：2023-09-11

Applicant: Macronix International Co., Ltd.

Inventor： Feng-Min Lee ,  Po-Hao Tseng ,  Yu-Yu Lin ,  Ming-Hsiu Lee

IPC: G06N3/063 ,  G11C11/405 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/54

Abstract: A universal memory device includes an array of universal memory cells. Each universal memory cell includes a write transistor and a read transistor. The write transistor has a gate terminal configured to receive a gate voltage to turn on or off the write transistor, a first terminal configured to receive a write voltage, and a second terminal coupled to a gate terminal of the read transistor. The read transistor includes a charge trap layer at the gate terminal of the read transistor. The charge trap layer is configured to: be unalterable when the first write voltage is applied at the first terminal of the write transistor, and be alterable when the second write voltage is applied at the first terminal of the write transistor to change a threshold voltage of the read transistor. The second write voltage is greater than the first write voltage.

公开(公告)号：US20250014635A1

公开(公告)日：2025-01-09

申请号：US18347571

申请日：2023-07-06

Applicant: MACRONIX International Co., Ltd.

Inventor： Po-Hao Tseng ,  Shao Yu Fang

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4094

Abstract: An in memory searching device, including multiple first memory cell strings, a controller, and a sensing circuit, is provided. The first memory cell strings are commonly coupled to a first common bit line. Each of the first memory strings includes multiple first data storage layers. The first data storage layers respectively include multiple first memory cell pairs. The first memory cell pairs are respectively coupled to multiple first word line pairs. The controller selects at least one of the first data storage layers to be at least one selected data storage layer, and provides search data to at least one selected word line pair corresponding to the at least one selected data storage layer. The sensing circuit senses a current on the first common bit line to generate a search result.

公开(公告)号：US12142319B2

公开(公告)日：2024-11-12

申请号：US17846304

申请日：2022-06-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao Tseng ,  Tian-Cih Bo ,  Feng-Min Lee

IPC: G11C15/04

Abstract: A hybrid type content addressable memory for implementing in-memory-search and an operation method thereof are provided. The CAM includes a plurality of CAM strings and at least one sense amplifier circuit. Each of the CAM strings includes a plurality of CAM cells. The CAM cells store a plurality of existing data. The sense amplifier circuit is connected to the CAM strings. A plurality of search data are inputted to the CAM strings. A plurality of cell matching results obtained from the CAM cells in each of the CAM strings are integrated via an AND operation to obtain a string matching result. The string matching results obtained from the CAM strings are integrated via an OR operation.

公开(公告)号：US20240274199A1

公开(公告)日：2024-08-15

申请号：US18166484

申请日：2023-02-09

Applicant: MACRONIX International Co., Ltd.

Inventor： Yu-Hsuan Lin ,  Po-Hao Tseng

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/26

Abstract: A hyperdimensional computing device includes a non-volatile memory cell array and a first operation circuit. The non-volatile memory cell array is coupled to a plurality of first word lines. The non-volatile memory cell array has a plurality of memory cell groups, a plurality of first memory cells of each of the memory cell groups are coupled to a same first word line of the first word lines, and the memory cell groups respectively store a plurality of data vectors. The first operation circuit receives at least one of the data vectors through bit lines and generates a bundled data vector according to the at least one of the data vectors.