公开(公告)号：US4780750A

公开(公告)日：1988-10-25

申请号：US815869

申请日：1986-01-03

申请人： Joseph G. Nolan ,  Michael A. Van Buskirk ,  Te-Long Chiu ,  Ying K. Shum

发明人： Joseph G. Nolan ,  Michael A. Van Buskirk ,  Te-Long Chiu ,  Ying K. Shum

IPC分类号： H01L21/8247 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/112 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78

CPC分类号： H01L29/7883

摘要： In this invention, an Electrically Alterable Non-Volatile Memory (EANOM) cell is disclosed. The EANOM ceil comprises an MOS transistor, having a source, a gate and a drain. The EANOM cell also has a two-terminal tunnel device, one end of which is connected to the gate of the MOS transistor. The other terminal being labelled "T". The tunnel device causes charges to be stored or removed from the gate of the MOS transistor. In a preferred embodiment, a four-terminal EANOM cell is disclosed. The four terminals of the EANOM cell are terminals T, S (source of the MOS transistor), D (drain of the MOS transistor) and a terminal C which is capacitively coupled to the gate of the MOS transistor. The EANOM cell can be used in a memory circuit to increase the reliability thereof. Two or more EANOM cells are connected in tandem and operate simultaneously. Catastrophic failure of one EANOM cell results in an open circuit with the other EANOM cell continuing to function.

摘要翻译： 在本发明中，公开了电可变非易失性存储器（EANOM）单元。 EANOM ceil包括具有源极，栅极和漏极的MOS晶体管。 EANOM单元还具有两端隧道器件，其一端连接到MOS晶体管的栅极。 另一个终端标记为“T”。 隧道装置使电荷从MOS晶体管的栅极存储或去除。 在优选实施例中，公开了四端子EANOM单元。 EANOM单元的四个端子是端子T，S（MOS晶体管的源极），D（MOS晶体管的漏极）和与MOS晶体管的栅极电容耦合的端子C. EANOM单元可用于存储器电路中以提高其可靠性。 两个或多个EANOM单元串联连接并同时操作。 一个EANOM细胞的灾难性故障导致另一个EANOM细胞继续发挥功能的开路。

公开(公告)号：US08748959B2

公开(公告)日：2014-06-10

申请号：US12751245

申请日：2010-03-31

申请人： Michael A. Van Buskirk ,  Christian Caillat ,  Viktor I Koldiaev ,  Jungtae Kwon ,  Pierre C. Fazan

发明人： Michael A. Van Buskirk ,  Christian Caillat ,  Viktor I Koldiaev ,  Jungtae Kwon ,  Pierre C. Fazan

IPC分类号： H01L27/108 ,  H01L21/762

CPC分类号： H01L29/1095 ,  H01L21/76264 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10891 ,  H01L29/7841

摘要： A semiconductor memory device is disclosed. In one particular exemplary embodiment, the semiconductor memory device includes a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation. Each memory cell may also include a second region connected to a bit line extending a second orientation. Each memory cell may further include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation and a second barrier wall extending in the second orientation and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.

摘要翻译： 公开了一种半导体存储器件。 在一个特定的示例性实施例中，半导体存储器件包括以行和列的阵列排列的多个存储器单元。 每个存储单元可以包括连接到沿第一取向延伸的源极线的第一区域。 每个存储单元还可以包括连接到延伸第二取向的位线的第二区域。 每个存储器单元还可以包括与字线间隔开并且电容耦合到字线的主体区域，其中所述主体区域电浮动并且设置在所述第一区域和所述第二区域之间。 半导体器件还可以包括在第一取向上延伸的第一阻挡壁和在第二取向上延伸并与第一阻挡壁相交的第二阻挡壁，以形成配置成容纳多个存储单元中的每一个的沟槽区。

公开(公告)号：US08498157B2

公开(公告)日：2013-07-30

申请号：US12785971

申请日：2010-05-24

申请人： Srinivasa Rao Banna ,  Michael A. Van Buskirk

发明人： Srinivasa Rao Banna ,  Michael A. Van Buskirk

IPC分类号： G11C16/04

CPC分类号： G11C7/00 ,  G11C11/4026 ,  G11C11/403 ,  G11C2211/4016 ,  H01L27/082 ,  H01L27/1023 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

摘要： Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region connected to a bit line extending in a first orientation and a second region connected to a source line extending in a second orientation. The direct injection semiconductor memory device may also include a body region spaced apart from and capacitively coupled to a word line extending in the second orientation, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further include a third region connected to a carrier injection line extending in the second orientation, wherein the first region, the second region, the body region, and the third region are disposed in sequential contiguous relationship.

公开(公告)号：US20120294083A1

公开(公告)日：2012-11-22

申请号：US13109821

申请日：2011-05-17

申请人： Srinivasa Rao Banna ,  Michael A. Van Buskirk ,  Timothy Thurgate

发明人： Srinivasa Rao Banna ,  Michael A. Van Buskirk ,  Timothy Thurgate

IPC分类号： G11C14/00

CPC分类号： G11C16/0441 ,  G11C16/0475 ,  G11C16/0483 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7889

摘要： Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns, each memory cell. Each of the memory cell may include a first region coupled to a source line, a second region coupled to a bit line, and a body region capacitively coupled to at least one word line via a gate region and disposed between the first region and the second region, wherein the body region may include a plurality of floating body regions and a plurality of floating gate regions capacitively coupled to the at least one word line.

摘要翻译： 公开了一种用于提供半导体存储器件的技术。 在一个特定实施例中，这些技术可被实现为半导体存储器件，其包括布置成行和列阵列的多个存储器单元，每个存储器单元。 每个存储单元可以包括耦合到源极线的第一区域，耦合到位线的第二区域和经由栅极区域电容耦合到至少一个字线并且被布置在第一区域和第二区域之间的体区域 区域，其中所述主体区域可以包括多个浮动体区域和电容耦合到所述至少一个字线的多个浮动栅极区域。

公开(公告)号：US20110222356A1

公开(公告)日：2011-09-15

申请号：US13047097

申请日：2011-03-14

申请人： Srinivasa Rao Banna ,  Michael A. Van Buskirk ,  Timothy Thurgate

发明人： Srinivasa Rao Banna ,  Michael A. Van Buskirk ,  Timothy Thurgate

IPC分类号： G11C7/00 ,  H01L27/105

CPC分类号： H01L27/10802 ,  G11C7/00 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/1029 ,  H01L29/1095 ,  H01L29/7841

摘要： Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.

摘要翻译： 公开了一种用于提供半导体存储器件的技术。 在一个特定示例性实施例中，这些技术可以被实现为包括布置成行和列阵列的多个存储器单元的半导体存储器件。 每个存储单元包括电容耦合到至少一个字线并且设置在第一区域和第二区域之间的第一区域，第二区域和体区域。 每个存储单元还包括第三区域，其中第三区域可以掺杂不同于第一区域，第二区域和体区域。

公开(公告)号：US20100271858A1

公开(公告)日：2010-10-28

申请号：US12768363

申请日：2010-04-27

申请人： Eric Scott Carman ,  Michael A. Van Buskirk ,  Yogesh Luthra

发明人： Eric Scott Carman ,  Michael A. Van Buskirk ,  Yogesh Luthra

IPC分类号： G11C5/06 ,  G11C7/00

CPC分类号： H01L27/0664 ,  G11C5/025 ,  G11C5/06 ,  G11C5/063 ,  G11C7/00 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4074 ,  G11C11/4094 ,  G11C2211/4016 ,  H01L29/7302 ,  H01L29/732

摘要： Techniques for providing a direct injection semiconductor memory device having ganged carrier injection lines are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region coupled to a bit line and a second region coupled to a source line. The apparatus may also comprise a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The apparatus may further comprise a third region coupled to a constant voltage source via a carrier injection line configured to inject charges into the body region through the second region.

摘要翻译： 公开了一种用于提供具有联动载体注入管线的直接注入半导体存储器件的技术。 在一个特定示例性实施例中，技术可以被实现为包括耦合到位线的第一区域和耦合到源极线的第二区域的装置。 该装置还可以包括与字线间隔开并电容耦合到字线的主体区域，其中主体区域电浮动并且设置在第一区域和第二区域之间。 该装置还可以包括经由载体注入管线耦合到恒定电压源的第三区域，其被配置为通过第二区域将电荷注入体区域。

公开(公告)号：US07474579B2

公开(公告)日：2009-01-06

申请号：US11613832

申请日：2006-12-20

申请人： Colin S. Bill ,  Swaroop Kaza ,  Wei Daisy Cai ,  Tzu-Ning Fang ,  David Gaun ,  Eugen Gershon ,  Michael A. Van Buskirk ,  Jean Wu

发明人： Colin S. Bill ,  Swaroop Kaza ,  Wei Daisy Cai ,  Tzu-Ning Fang ,  David Gaun ,  Eugen Gershon ,  Michael A. Van Buskirk ,  Jean Wu

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40615 ,  G11C13/0033 ,  G11C13/0069 ,  G11C16/3431

摘要： Systems and methods are disclosed that facilitate extending data retention time in a data retention device, such as a nanoscale resistive memory cell array, via assessing a resistance level in a tracking element associated with the memory array and refreshing the memory array upon a determination that the resistance of the tracking element has reached or exceeded a predetermined reference threshold resistance value. The tracking element can be a memory cell within the array itself and can have an initial resistance value that is substantially higher than an initial resistance value for a programmed memory cell in the array, such that resistance increase in the tracking cell will cause the tracking cell to reach the threshold value and trigger refresh of the array before data corruption/loss occurs in the core memory cells.

摘要翻译： 公开了通过评估与存储器阵列相关联的跟踪元件中的电阻水平并在确定存储器阵列的情况下刷新存储器阵列时有助于在诸如纳米级电阻存储器单元阵列之类的数据保持装置中扩展数据保留时间的系统和方法 跟踪元件的电阻已达到或超过预定参考阈值电阻值。 跟踪元件可以是阵列本身内的存储器单元，并且可以具有基本上高于阵列中的编程存储器单元的初始电阻值的初始电阻值，使得跟踪单元中的电阻增加将导致跟踪单元 在核心存储器单元中发生数据损坏/丢失之前达到阈值并触发阵列刷新。

公开(公告)号：US06510082B1

公开(公告)日：2003-01-21

申请号：US09999869

申请日：2001-10-23

申请人： Binh Q. Le ,  Pau-Ling Chen ,  Michael A. Van Buskirk ,  Santosh K. Yachareni ,  Michael S. C. Chung ,  Kazuhiro Kurihara ,  Shane Hollmer

发明人： Binh Q. Le ,  Pau-Ling Chen ,  Michael A. Van Buskirk ,  Santosh K. Yachareni ,  Michael S. C. Chung ,  Kazuhiro Kurihara ,  Shane Hollmer

IPC分类号： G11C1604

CPC分类号： G11C16/0491 ,  G11C16/28

摘要： A system is disclosed for producing an indication of the logical state of a flash memory cell for virtual ground flash memory operations. The system comprises a bit line charge and hold circuit which is operable to apply a read sense voltage (e.g., about 1.2 volts) to a bit line associated with the drain terminal of a cell of the flash array adjacent to the cell which is sensed, wherein the applied drain terminal voltage is substantially the same as the cell sense voltage (e.g., about 1.2 volts) applied to the drain terminal bit line of the selected memory cell to be sensed. The system further includes a selective bit line decode circuit which is operable to select the bit lines of a memory cell to be sensed and the bit line of an adjacent cell, and a core cell sensing circuit which is operable to sense a core cell sense current at a bit line associated with a drain terminal of the selected memory cell to be sensed during memory read operations, and produce an indication of the flash memory cell logical state, which is substantially independent of charge sharing leakage current to an adjacent cell.

摘要翻译： 公开了一种用于产生用于虚拟接地闪速存储器操作的闪存单元的逻辑状态的指示的系统。 该系统包括位线充电和保持电路，其可操作以将读取感测电压（例如，约1.2伏特）施加到与所感测的电池相邻的闪光阵列的单元的漏极端子相关联的位线， 其中所施加的漏极端子电压基本上与施加到要被感测的所选择的存储器单元的漏极端子位线的单元检测电压（例如，约1.2伏特）相同。 该系统还包括选择性位线解码电路，其可操作以选择要感测的存储器单元的位线和相邻单元的位线;以及核心单元感测电路，其可操作以感测核心单元感测电流 在与存储器读取操作期间被感测的所选择的存储器单元的漏极端子相关联的位线处，并产生闪存单元逻辑状态的指示，其基本上与相邻单元的电荷共享泄漏电流无关。

公开(公告)号：US06493261B1

公开(公告)日：2002-12-10

申请号：US09795865

申请日：2001-02-28

申请人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Ravi Sunkavalli ,  Narbeh Derhacobian ,  Michael A. Van Buskirk

发明人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Ravi Sunkavalli ,  Narbeh Derhacobian ,  Michael A. Van Buskirk

IPC分类号： G11C1604

CPC分类号： G11C16/3409 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/344 ,  G11C16/3445 ,  H01L27/115

摘要： Dummy columns of memory cells formed during fabrication outside edge columns are connected to the actual used memory cells of sectors or the like. The columns of dummy memory cells are compensated by floating the dummy memory cells during normal programming and erase cycles, or alternatively, by programming and erasing the dummy memory cells along with the actual used memory cells in the sector. By treating the dummy memory cells similar to the actual used cells, charge that leaks into the dummy cells during fabrication and normal operation that has deleterious effects at higher stress temperatures and/or due to the longevity of customer operation is substantially eliminated.

摘要翻译： 在制造外边缘列时形成的存储单元的虚拟柱被连接到扇区等的实际使用的存储单元。 虚拟存储单元的列通过在正常编程和擦除周期期间浮置伪存储单元来补偿，或者通过编程和擦除虚存储单元以及扇区中的实际使用的存储单元来补偿。 通过处理类似于实际使用的电池的虚拟存储器单元，在制造和正常操作期间泄漏到虚拟电池中的电荷在较高应力温度和/或由于客户操作的寿命而具有有害影响的基本上被消除。

公开(公告)号：US06465306B1

公开(公告)日：2002-10-15

申请号：US09723635

申请日：2000-11-28

申请人： Mark T. Ramsbey ,  Jean Y. Yang ,  Hidehiko Shiraiwa ,  Michael A. Van Buskirk ,  David M. Rogers ,  Ravi Sunkavalli ,  Janet Wang ,  Narbeh Derhacobian ,  Yider Wu

发明人： Mark T. Ramsbey ,  Jean Y. Yang ,  Hidehiko Shiraiwa ,  Michael A. Van Buskirk ,  David M. Rogers ,  Ravi Sunkavalli ,  Janet Wang ,  Narbeh Derhacobian ,  Yider Wu

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  Y10S438/954 ,  Y10S438/981

摘要： One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; and forming gates in the core region and the periphery region.

摘要翻译： 本发明的一个方面涉及一种形成非挥发性半导体存储器件的方法，涉及在衬底上形成电荷俘获电介质的顺序或非顺序步骤，所述衬底具有芯区域和外围区域; 去除外围区域中的电荷捕获电介质的至少一部分; 在周边区域形成栅电介质; 在核心区域形成掩埋位线; 并且在芯区域和周边区域中形成栅极。