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公开(公告)号：US20090209097A1
公开(公告)日：2009-08-20
申请号：US12032295
申请日：2008-02-15
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/0273 , H01L21/0338 , H01L21/31144
摘要： A method of forming interconnects includes etching a first set of openings in a hard mask using a first photo resist layer with a first pattern of openings as a first etch mask, and etching a second set of openings in the hard mask using a second photo resist layer with a second pattern of openings as a second etch mask. The method includes shrinking the openings in at least one of the first pattern and the second pattern prior to etching the openings in the hard mask.
摘要翻译： 一种形成互连的方法包括使用具有第一开口图案的第一光致抗蚀剂层作为第一蚀刻掩模蚀刻在硬掩模中的第一组开口，以及使用第二光致抗蚀剂蚀刻硬掩模中的第二组开口 层，其具有作为第二蚀刻掩模的第二开口图案。 该方法包括在蚀刻硬掩模中的开口之前收缩第一图案和第二图案中的至少一个中的开口。
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公开(公告)号：US20090134497A1
公开(公告)日：2009-05-28
申请号：US11944846
申请日：2007-11-26
申请人： Hans-Joachim Barth , Jens Pohl
发明人： Hans-Joachim Barth , Jens Pohl
IPC分类号： H01L29/417 , H01L21/441
CPC分类号： H01L21/76898 , H01L23/481 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/131 , H01L2924/0002 , H01L2924/014 , H01L2224/05552
摘要： A structure and method of forming landing pads for through substrate vias in forming stacked semiconductor components are described. In various embodiments, the current invention describes landing pad structures that includes multiple levels of conductive plates connected by vias such that the electrical connection between a through substrate etch and landing pad is independent of the location of the bottom of the through substrate trench.
摘要翻译： 描述了在形成堆叠的半导体部件中形成通过衬底通孔的着陆焊盘的结构和方法。 在各种实施例中，本发明描述着陆焊盘结构，其包括通过通孔连接的多层导电板，使得贯穿衬底蚀刻和着陆焊盘之间的电连接独立于贯穿衬底沟槽的底部的位置。
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公开(公告)号：US20090073633A1
公开(公告)日：2009-03-19
申请号：US11856775
申请日：2007-09-18
CPC分类号： H01L23/5223 , H01G4/33 , H01L28/40 , H01L2924/0002 , Y10T29/435 , H01L2924/00
摘要： One or more embodiments are related to a semiconductor structure, comprising: a semiconductor chip having a final metal layer; a dielectric layer disposed over the final metal layer; and a conductive layer deposed over the dielectric layer, the dielectric layer being between the final metal layer and the conductive layer.
摘要翻译： 一个或多个实施例涉及半导体结构，包括：具有最终金属层的半导体芯片; 设置在最终金属层上的电介质层; 并且导电层设置在电介质层之上，介电层位于最终的金属层和导电层之间。
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公开(公告)号：US20090072411A1
公开(公告)日：2009-03-19
申请号：US11855170
申请日：2007-09-14
CPC分类号： H01L23/5389 , H01L23/3121 , H01L23/49838 , H01L23/645 , H01L24/24 , H01L24/82 , H01L24/96 , H01L28/10 , H01L2224/24137 , H01L2224/24195 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/04953 , H01L2924/181 , H01L2924/18162 , H01L2924/19042 , H01L2924/19104 , H01L2924/30107 , H01L2924/00
摘要： One or more embodiments are related to a semiconductor structure, comprising: a semiconductor chip; a conductive layer comprising at least a first conductive pathway and a second conductive pathway spacedly disposed from the first conductive pathway, the first conductive pathway electrically coupled to the chip, at least a portion of the first conductive pathway disposed outside the lateral boundary of the chip, at least a portion of the second conductive pathway disposed outside the lateral boundary of the chip; and a conductive interconnect disposed outside the lateral boundary of the chip, the conductive interconnect electrically coupling the first conductive pathway to the second conductive pathway.
摘要翻译： 一个或多个实施例涉及半导体结构，包括：半导体芯片; 导电层，包括至少第一导电路径和与第一导电路径间隔设置的第二导电路径，第一导电路径电耦合到芯片，第一导电路径的至少一部分设置在芯片的横向边界外侧 所述第二导电通路的至少一部分设置在所述芯片的横向边界的外侧; 以及布置在所述芯片的横向边界外侧的导电互连，所述导电互连将所述第一导电路径电耦合到所述第二导电路径。
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公开(公告)号：US20090072388A1
公开(公告)日：2009-03-19
申请号：US11856089
申请日：2007-09-17
CPC分类号： H01L23/5389 , H01L23/5388 , H01L24/82 , H01L24/96 , H01L2224/04105 , H01L2224/12105 , H01L2224/24195 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01046 , H01L2924/01047 , H01L2924/01058 , H01L2924/01059 , H01L2924/01063 , H01L2924/01064 , H01L2924/01066 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01105 , H01L2924/181 , H01L2924/18162 , H01L2924/00
摘要： One or more embodiments are directed to a semiconductor structure, comprising: a support; a semiconductor chip at least partially embedded within the support; and an inductor electrically coupled to the chip, at least a portion of the inductor overlying the support outside the lateral boundary of the chip.
摘要翻译： 一个或多个实施例涉及半导体结构，包括：支撑件; 至少部分地嵌入所述支撑件内的半导体芯片; 以及电耦合到所述芯片的电感器，所述电感器的至少一部分覆盖在所述芯片的横向边界外侧的所述支撑件。
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公开(公告)号：US07440334B2
公开(公告)日：2008-10-21
申请号：US11387490
申请日：2006-03-23
IPC分类号： G11C11/34
CPC分类号： G11C11/405 , H01L27/108 , H01L27/1104
摘要： A memory cell having three transistors and a capacitor having metallic electrodes is described. Multiple memory cells may be arranged in a memory unit or array. Collective electrodes may be used in a space-saving embodiment of the capacitor.
摘要翻译： 描述具有三个晶体管的存储单元和具有金属电极的电容器。 多个存储器单元可以被布置在存储器单元或阵列中。 集电极可以用在电容器的节省空间的实施例中。
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公开(公告)号：US20080186788A1
公开(公告)日：2008-08-07
申请号：US11670770
申请日：2007-02-02
申请人： Hans-Joachim Barth
发明人： Hans-Joachim Barth
IPC分类号： G11C17/18 , H01L23/525
CPC分类号： H01L23/5256 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： A fuse link of undoped material is connected between first and second doped material contact regions and a layer of conductive material is located above the first and second contact regions and the fuse link. According to other embodiments, a fuse link is connected between first and second contact regions. A layer of conductive material is above the first and second contact regions and the fuse link, and a heat sink is in proximity to the fuse link. In a method, a programming pulse is applied to a fuse link of undoped material connected between first and second doped material contact regions to generate electromigration drift of a conductive material above the first and second contact regions and the fuse link.
摘要翻译： 未掺杂材料的熔丝连接在第一和第二掺杂材料接触区域之间，并且导电材料层位于第一和第二接触区域和熔丝链的上方。 根据其他实施例，熔丝链路连接在第一和第二接触区域之间。 导电材料层位于第一和第二接触区域和熔断体之上，散热器靠近熔断体。 在一种方法中，将编程脉冲施加到连接在第一和第二掺杂材料接触区域之间的未掺杂材料的熔丝链，以在第一和第二接触区域和熔丝链上方产生导电材料的电迁移漂移。
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公开(公告)号：US20060014374A1
公开(公告)日：2006-01-19
申请号：US10518880
申请日：2003-06-03
申请人： Hans-Joachim Barth , Recai Sezi
发明人： Hans-Joachim Barth , Recai Sezi
IPC分类号： H01L21/4763
CPC分类号： H01L21/768 , H01L21/7682 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a layer arrangement and to a process for producing a layer arrangement. The layer arrangement has a layer which is arranged on a substrate and includes a first subregion comprising decomposable material and a second subregion which is arranged next to the first subregion and has a useful structure comprising a non-decomposable material. Furthermore, the layer arrangement has a covering layer on the layer comprising decomposable material and the useful structure, the layer arrangement being designed in such a manner that the decomposable material can be removed from the layer arrangement.
摘要翻译： 本发明涉及层布置和用于生产层布置的方法。 层布置具有布置在基板上的层，并且包括第一子区域，其包括可分解材料，第二子区域布置在第一子区域旁边，并且具有包含不可分解材料的有用结构。 此外，层布置在包括可分解材料和有用结构的层上具有覆盖层，层布置被设计成使得可分解材料可以从层布置中移除。
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49.发明申请Method for producing thin metal-containing layers having a low electrical resistance 审中-公开具有低电阻的含薄金属层的制造方法公开(公告)号：US20050064705A1
公开(公告)日：2005-03-24
申请号：US10495110
申请日：2002-09-09
申请人： Hans-Joachim Barth
发明人： Hans-Joachim Barth
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76838
摘要： The invention relates to a process for producing metal-containing thin films with a low electrical resistance, in which first of all a metal-containing layer (5′) with a first grain size is formed up to a recrystallization thickness (d1), and then, at this recrystallization thickness (d1), a recrystallization is carried out in order to produce a metal-containing layer (5″) with a larger grain size. Finally, the metal-containing layer (5″) with the larger grain size is thinned to a desired target thickness (d2), resulting in a very thin metal-containing layer with an electrical resistance which is reduced further.
摘要翻译： 本发明涉及一种具有低电阻的含金属薄膜的制造方法，其中首先形成具有第一晶粒尺寸的含金属层（5'）至再结晶厚度（d1），以及 然后，在该再结晶厚度（d1）下，进行再结晶以制造具有较大晶粒尺寸的含金属层（5“）。 最后，将具有较大晶粒尺寸的含金属层（5“）减薄至所需目标厚度（d2），导致非常薄的含金属层，其电阻进一步降低。
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公开(公告)号：US06559042B2
公开(公告)日：2003-05-06
申请号：US09894337
申请日：2001-06-28
IPC分类号： H01L213205
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A process for forming fusible links in an integrated circuit includes forming the fusible link in the last metallization layer. The process can be employed in the fabrication of integrated circuits employing copper metallization and low k dielectric materials. The fusible link is formed in the last metallization layer and may be formed simultaneously with the bonding pad areas.
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