公开(公告)号：US20060014374A1

公开(公告)日：2006-01-19

申请号：US10518880

申请日：2003-06-03

申请人： Hans-Joachim Barth ,  Recai Sezi

发明人： Hans-Joachim Barth ,  Recai Sezi

IPC分类号： H01L21/4763

CPC分类号： H01L21/768 ,  H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention relates to a layer arrangement and to a process for producing a layer arrangement. The layer arrangement has a layer which is arranged on a substrate and includes a first subregion comprising decomposable material and a second subregion which is arranged next to the first subregion and has a useful structure comprising a non-decomposable material. Furthermore, the layer arrangement has a covering layer on the layer comprising decomposable material and the useful structure, the layer arrangement being designed in such a manner that the decomposable material can be removed from the layer arrangement.

摘要翻译： 本发明涉及层布置和用于生产层布置的方法。 层布置具有布置在基板上的层，并且包括第一子区域，其包括可分解材料，第二子区域布置在第一子区域旁边，并且具有包含不可分解材料的有用结构。 此外，层布置在包括可分解材料和有用结构的层上具有覆盖层，层布置被设计成使得可分解材料可以从层布置中移除。

公开(公告)号：US09245799B2

公开(公告)日：2016-01-26

申请号：US13484352

申请日：2012-05-31

申请人： Hans-Joachim Barth

发明人： Hans-Joachim Barth

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/108 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L21/02203 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76828 ,  H01L21/76831 ,  H01L21/76895 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

摘要： A semiconductor device includes a substrate having a top surface. A semiconductor circuit defines a circuit area on the top surface of the substrate. An interconnect is spaced apart from the circuit area and extends from the top surface into the substrate. The interconnect includes a sidewall formed of an electrically insulating material. An opening is provided in the sidewall.

摘要翻译： 半导体器件包括具有顶表面的衬底。 半导体电路限定了衬底的顶表面上的电路区域。 互连件与电路区域间隔开并从顶表面延伸到衬底中。 互连包括由电绝缘材料形成的侧壁。 在侧壁中设置开口。

公开(公告)号：US09012297B2

公开(公告)日：2015-04-21

申请号：US12876866

申请日：2010-09-07

申请人： Hans-Joachim Barth ,  Helmut Horst Tews

发明人： Hans-Joachim Barth ,  Helmut Horst Tews

IPC分类号： H01L21/441 ,  H01L27/08 ,  H01L23/522 ,  H01L23/00 ,  H01L23/58 ,  H01L27/06

CPC分类号： H01L28/75 ,  G06F17/5068 ,  H01L21/76897 ,  H01L22/14 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/562 ,  H01L23/585 ,  H01L27/0611 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

摘要： Structures and methods of forming moisture barrier capacitor on a semiconductor component are disclosed. The capacitor is located on the periphery of a semiconductor chip and includes an inner plate electrically connected to a voltage node, an outer plate with fins for electrically connecting to a different voltage node.

摘要翻译： 公开了在半导体部件上形成防潮电容器的结构和方法。 电容器位于半导体芯片的周围，并且包括电连接到电压节点的内板，具有用于电连接到不同电压节点的翅片的外板。

公开(公告)号：US20140291819A1

公开(公告)日：2014-10-02

申请号：US13854449

申请日：2013-04-01

申请人： Hans-Joachim Barth

发明人： Hans-Joachim Barth

IPC分类号： H01L23/532 ,  H01L23/552 ,  H01L21/768

CPC分类号： H01L51/0048 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/768 ,  H01L21/76805 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76879 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49872 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/53276 ,  H01L23/645 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L29/1606 ,  H01L2221/1094 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2924/12032 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00

摘要： Embodiments of the present disclosure are directed towards techniques and configurations for hybrid carbon-metal interconnect structures in integrated circuit assemblies. In one embodiment, an apparatus includes a substrate, a metal interconnect layer disposed on the substrate and configured to serve as a growth initiation layer for a graphene layer and the graphene layer, wherein the graphene layer is formed directly on the metal interconnect layer, the metal interconnect layer and the graphene layer being configured to route electrical signals. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例涉及集成电路组件中的混合碳 - 金属互连结构的技术和配置。 在一个实施例中，一种装置包括衬底，设置在衬底上并被配置为用作石墨烯层和石墨烯层的生长起始层的金属互连层，其中石墨烯层直接形成在金属互连层上， 金属互连层和石墨烯层被配置为路由电信号。 可以描述和/或要求保护其他实施例。

公开(公告)号：US08138539B2

公开(公告)日：2012-03-20

申请号：US11947591

申请日：2007-11-29

申请人： Hans-Joachim Barth ,  Erwin Ruderer ,  Alexander Von Glasow ,  Philipp Riess ,  Erdem Kaltalioglu ,  Peter Baumgartner ,  Thomas Benetik ,  Helmut Horst Tews

发明人： Hans-Joachim Barth ,  Erwin Ruderer ,  Alexander Von Glasow ,  Philipp Riess ,  Erdem Kaltalioglu ,  Peter Baumgartner ,  Thomas Benetik ,  Helmut Horst Tews

IPC分类号： H01L27/108 ,  H01L21/20

CPC分类号： H01L27/0805 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.

摘要翻译： 公开了半导体器件及其制造方法。 在一个实施例中，电容器板包括多个第一平行导电构件，以及设置在多个第一平行导电构件上的多个第二平行导电构件。 第一基座构件联接到多个第一平行导电构件的端部，并且第二基座构件联接到多个第二平行导电构件的端部。 连接构件设置在多个第一平行导电构件和多个第二平行导电构件之间，其中连接构件包括至少一个细长通孔。

公开(公告)号：US07986033B2

公开(公告)日：2011-07-26

申请号：US12124335

申请日：2008-05-21

申请人： Hans-Joachim Barth

发明人： Hans-Joachim Barth

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L23/34 ,  H01L2225/06513 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/00

摘要： A three-dimensional multichip module includes a first integrated circuit chip having at least one first high-temperature functional area and one first low-temperature functional area, and at least one second integrated circuit chip having a second high-temperature functional area and a second low-temperature functional area. The second high-temperature functional area is arranged opposite the first low-temperature functional area. As an alternative, at least one low-temperature chip having only one low-temperature functional area can also be arranged between the first and second chips.

摘要翻译： 三维多芯片模块包括具有至少一个第一高温功能区和一个第一低温功能区的第一集成电路芯片和至少一个具有第二高温功能区和第二高温功能区的第二集成电路芯片 低温功能区。 第二高温功能区与第一低温功能区相对。 作为替代，也可以在第一和第二芯片之间设置至少一个仅具有一个低温功能区的低温芯片。

公开(公告)号：US07948064B2

公开(公告)日：2011-05-24

申请号：US12242698

申请日：2008-09-30

申请人： Hans-Joachim Barth ,  Andre Hanke ,  Snezana Jenei ,  Oliver Nagy ,  Jiro Morinaga ,  Bernd Adler ,  Heinrich Koerner

发明人： Hans-Joachim Barth ,  Andre Hanke ,  Snezana Jenei ,  Oliver Nagy ,  Jiro Morinaga ,  Bernd Adler ,  Heinrich Koerner

IPC分类号： H01L23/552 ,  H01L21/71

CPC分类号： H01L21/71 ,  H01L23/49822 ,  H01L23/552 ,  H01L23/585 ,  H01L23/66 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

摘要： Structures of a system on a chip are disclosed. In one embodiment, the system on a chip (SoC) includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary, and a conductive cage disposed enclosing the RF component. The conductive cage shields the semiconductor component from electromagnetic radiation originating from the RF circuit.

摘要翻译： 公开了一种芯片上的系统的结构。 在一个实施例中，芯片上的系统（SoC）包括设置在基板的第一部分上的RF部件，设置在基板的第二部分上的半导体部件，共享公共边界的半导体部件和RF部件，以及 布置成围绕RF部件的导电笼。 导电笼罩半导体元件不受来自RF电路的电磁辐射。

公开(公告)号：US07812424B2

公开(公告)日：2010-10-12

申请号：US11962395

申请日：2007-12-21

申请人： Hans-Joachim Barth ,  Helmut Horst Tews

发明人： Hans-Joachim Barth ,  Helmut Horst Tews

IPC分类号： H01L29/92

CPC分类号： H01L28/75 ,  G06F17/5068 ,  H01L21/76897 ,  H01L22/14 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/562 ,  H01L23/585 ,  H01L27/0611 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

摘要： Structures and methods of forming moisture barrier capacitor on a semiconductor component are disclosed. The capacitor is located on the periphery of a semiconductor chip and includes an inner plate electrically connected to a voltage node, an outer plate with fins for electrically connecting to a different voltage node.

摘要翻译： 公开了在半导体部件上形成防潮电容器的结构和方法。 电容器位于半导体芯片的周围，并且包括电连接到电压节点的内板，具有用于电连接到不同电压节点的翅片的外板。

公开(公告)号：US20100176479A1

公开(公告)日：2010-07-15

申请号：US12354480

申请日：2009-01-15

申请人： Sergei Postnikov ,  Thomas Schulz ,  Hans-Joachim Barth ,  Klaus von Arnim

发明人： Sergei Postnikov ,  Thomas Schulz ,  Hans-Joachim Barth ,  Klaus von Arnim

IPC分类号： H01L29/68 ,  H01L21/762

CPC分类号： H01L27/11 ,  G03F7/40 ,  G03F7/7035 ,  H01L21/32139

摘要： A method of fabricating a semiconductor device including depositing a hardmask layer on a layer of the semiconductor device, selectively etching a pattern of continuous lines in the hardmask layer, depositing an antireflective coating over remaining portions of the hardmask layer, depositing a photoresist layer on the antireflective coating, patterning the photoresist layer with a plurality of isolation trenches via a lithography process, each of the isolation trenches extending perpendicular to and crossing portions of at least one of the continuous lines of the underlying hardmask layer, and with each isolation trench having an initial width. The method further includes reducing the width of each of the isolation trenches from the initial width to desired width via a shrinking process, etching the antireflective coating underlying the isolation trenches to expose intersecting portions of the underlying continuous lines, and etching the exposed intersecting portions of the underlying continuous lines of the hardmask layer to form a pattern of line segments having line ends separated by the desired width.

摘要翻译： 一种制造半导体器件的方法，包括在半导体器件的层上沉积硬掩模层，选择性地蚀刻硬掩模层中的连续线的图案，在硬掩模层的剩余部分上沉积抗反射涂层，将光致抗蚀剂层沉积在 抗反射涂层，通过光刻工艺用多个隔离沟槽图案化光致抗蚀剂层，每个隔离沟槽垂直于并交叉下层硬掩模层的至少一条连续线的部分延伸，并且每个隔离沟槽具有 初始宽度。 该方法还包括通过收缩过程将每个隔离沟槽的宽度从初始宽度减小到期望宽度，蚀刻隔离沟槽下方的抗反射涂层以暴露下面的连续线的相交部分，并蚀刻暴露的相交部分 硬掩模层的下面的连续线以形成具有以期望宽度分隔的线端部的线段的图案。

公开(公告)号：US07755196B2

公开(公告)日：2010-07-13

申请号：US11857944

申请日：2007-09-19

申请人： Hans-Joachim Barth ,  Jurgen Holz

发明人： Hans-Joachim Barth ,  Jurgen Holz

IPC分类号： H01L23/48

CPC分类号： H01L23/5223 ,  H01L23/53238 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/48463 ,  H01L2924/14 ,  H01L2924/00

摘要： A method for production of an integrated circuit arrangement which contains a capacitor. A dielectric layer is structured with the aid of a two-stage etching process, and with the aid of a hard mask. In the case of an electrically insulating hard mask, the hard mask is removed again. In the case of an electrically conductive hard mask, parts of the hard mask may remain in the circuit arrangement.

摘要翻译： 一种用于制造包含电容器的集成电路装置的方法。 借助于两层蚀刻工艺，借助于硬掩模来构造电介质层。 在电绝缘硬掩模的情况下，再次去除硬掩模。 在导电硬掩模的情况下，硬掩模的部分可能保留在电路装置中。