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59 条记录 (耗时 0.028 秒)

    Optically sensitive device and method
    41.
    发明授权
    Optically sensitive device and method 失效
    光敏装置及方法

    公开(公告)号：US5886374A

    公开(公告)日：1999-03-23

    申请号：US2801

    申请日：1998-01-05

    申请人： Kurt K. Sakamoto ,  Peter J. Zdebel ,  Christopher K. Y. Chun

    发明人： Kurt K. Sakamoto ,  Peter J. Zdebel ,  Christopher K. Y. Chun

    IPC分类号： H01L27/144 ,  H01L31/062 ,  H01L31/075 ,  H01L31/105 ,  H01L31/113

    CPC分类号： H01L27/1443

    摘要： A process combines a high performance silicon pin diode (60) and other semiconductor devices such as transistors, resistors, and capacitors. The pin diode (60) is formed beneath an epitaxial layer (44) of the device at a depth that maximizes absorption of light having a wavelength greater than approximately 600 nanometers. Devices such as transistors are formed in the epitaxial layer (44). An integrated circuit has a substrate (41), an intrinsically doped layer (42), a buried layer (43), and an epitaxial layer (44). An isolation region (45) isolates an intrinsically doped region (46), a buried layer region (47), and the epitaxial layer region (48). The pin diode (32) has a substrate (41), an intrinsically doped region (46), and a buried layer region (47). A polysilicon region (62) provides a top side contact for the pin diode (60).

    摘要翻译： 一种工艺结合了高性能硅pin二极管（60）和诸如晶体管，电阻器和电容器的其它半导体器件。 pin二极管（60）形成在器件的外延层（44）的下方，其深度使得波长大于约600纳米的光的吸收最大化。 诸如晶体管的器件形成在外延层（44）中。 集成电路具有衬底（41），本征掺杂层（42），掩埋层（43）和外延层（44）。 隔离区域（45）隔离本征掺杂区域（46），掩埋层区域（47）和外延层区域（48）。 pin二极管（32）具有衬底（41），本征掺杂区域（46）和掩埋层区域（47）。 多晶硅区域（62）提供针二极管（60）的顶侧接触。

    Integrated circuit well bias circuitry
    43.
    发明授权
    Integrated circuit well bias circuitry 有权
    集成电路阱偏置电路

    公开(公告)号：US07170116B2

    公开(公告)日：2007-01-30

    申请号：US11168593

    申请日：2005-06-28

    申请人： Christopher K. Y. Chun ,  Der Yi Sheu

    发明人： Christopher K. Y. Chun ,  Der Yi Sheu

    IPC分类号： H01L27/10

    CPC分类号： H01L27/0203 ,  H03K19/0016

    摘要： Well bias circuitry for selectively biasing the voltages of the well areas of an integrated circuit. In one embodiment, the well bias circuitry includes a switching cell located in a row of cells of the integrated circuit for selectively coupling a voltage supply line to a well bias line. The switching cell may include two level shifters, each for providing a voltage to a gate of a coupling transistor to make the coupling transistor non conductive in response to an enable signal. The switching cells may be sequentially coupled such that the coupling transistors of each of the switching cells are not made conductive at the same time so as to reduce inrush current due to changing the well bias from a well bias voltage to a supply voltage. In one example, the switching cells may include delay circuitry for delaying the change in state of the enable signal before being provided to the next switching cell.

    摘要翻译： 用于选择性地偏置集成电路的阱区域的电压的良好偏置电路。 在一个实施例中，阱偏置电路包括位于集成电路的一行单元中的开关单元，用于选择性地将电压供应线耦合到阱偏置线。 开关单元可以包括两个电平移位器，每个电平移位器用于向耦合晶体管的栅极提供电压，以使得耦合晶体管响应于使能信号而不导通。 开关单元可以顺序耦合，使得每个开关单元的耦合晶体管不会同时导通，以便由于将阱偏压从阱偏置电压改变到电源电压来减少浪涌电流。 在一个示例中，开关单元可以包括延迟电路，用于在提供给下一个开关单元之前延迟使能信号的状态的改变。

    Method and circuitry for controlling supply voltage in a data processing system
    44.
    发明授权
    Method and circuitry for controlling supply voltage in a data processing system 有权
    用于控制数据处理系统中电源电压的方法和电路

    公开(公告)号：US07085943B2

    公开(公告)日：2006-08-01

    申请号：US10672161

    申请日：2003-09-26

    申请人： Christopher K. Y. Chun ,  Wayne W. Ballantyne ,  Gordon P. Lee ,  Scott A. Tassi ,  Darren V. Weninger

    发明人： Christopher K. Y. Chun ,  Wayne W. Ballantyne ,  Gordon P. Lee ,  Scott A. Tassi ,  Darren V. Weninger

    IPC分类号： G06F1/26

    CPC分类号： G06F1/3237 ,  G06F1/3203 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D50/20

    摘要： Supply voltages within a data processing system may be controlled by a voltage control module which can provide digital signals to a power management unit to cause changes in supply voltages without software intervention. For example, in one embodiment, a voltage control signal and a standby signal may be provided to control the supply voltages output by a voltage regulator within the power management unit. In one embodiment having multiple processors, a voltage control signal and a standby signal corresponding to each processor may be provided to the power management unit which has a voltage regulator supplying an independently controlled supply voltage to each processor. Alternatively, a voltage regulator, a voltage control signal, and a standby signal may be shared by multiple processors, where the voltage control module may ensure that the supply voltage is changed only when the change is appropriate for all processors sharing the same voltage regulator.

    摘要翻译： 数据处理系统内的电源电压可以由电压控制模块来控制，电压控制模块可以向电源管理单元提供数字信号，从而在没有软件干预的情况下引起电源电压的变化。 例如，在一个实施例中，可以提供电压控制信号和待机信号以控制由电力管理单元内的电压调节器输出的电源电压。 在具有多个处理器的一个实施例中，可以向功率管理单元提供对应于每个处理器的电压控制信号和待机信号，该电源管理单元具有向每个处理器提供独立控制的电源电压的电压调节器。 或者，电压调节器，电压控制信号和备用信号可以由多个处理器共享，其中电压控制模块可以确保仅当变化适用于共享相同电压调节器的所有处理器时才改变电源电压。

    Integrated circuit power management for reducing leakage current in circuit arrays and method therefor
    45.
    发明授权
    Integrated circuit power management for reducing leakage current in circuit arrays and method therefor 有权
    集成电路电源管理，用于减少电路阵列中的漏电流及其方法

    公开(公告)号：US06917555B2

    公开(公告)日：2005-07-12

    申请号：US10675005

    申请日：2003-09-30

    申请人： Ryan D. Bedwell ,  Christopher K. Y. Chun ,  Qadeer A. Qureshi ,  John J. Vaglica

    发明人： Ryan D. Bedwell ,  Christopher K. Y. Chun ,  Qadeer A. Qureshi ,  John J. Vaglica

    IPC分类号： G06F1/32 ,  G11C5/14 ,  G11C7/22 ,  G11C7/00

    CPC分类号： G06F1/3275 ,  G06F1/3203 ,  G11C5/14 ,  G11C7/22 ,  G11C2207/2227 ,  Y02D10/14

    摘要： Leakage current is eliminated in a memory array during a low power mode of a processing system having a processor that interfaces with the memory array. Because two power planes are created, the processor may continue executing instructions using a system memory while bypassing the memory array when the array is powered down. A switch selectively removes electrical connectivity to a supply voltage terminal in response to either processor-initiated control resulting from execution of an instruction or from a source originating in the system somewhere else than the processor. Upon restoration of power to the memory array, data may or may not need to be marked as unusable depending upon which of the two power planes supporting arrays to the memory array are located. Predetermined criteria may be used to control the timing of the restoration of power. Multiple arrays may be implemented to independently reduce leakage current.

    摘要翻译： 在具有与存储器阵列接口的处理器的处理系统的低功率模式期间，在存储器阵列中消除泄漏电流。 因为创建了两个电源平面，所以处理器可以在阵列掉电时绕过存储器阵列，继续执行使用系统存储器的指令。 开关选择性地去除与电源电压端子的电连接，以响应于执行指令或源自系统处于不同于处理器的系统的来源的处理器启动的控制。 在恢复对存储器阵列的电力的情况下，取决于支持阵列到存储器阵列的两个电力平面中的哪一个位于何处，数据可能也可能不需要被标记为不可用。 可以使用预定的标准来控制恢复电力的时间。 可以实现多个阵列以独立地减少泄漏电流。

    Differential charge and dump optoelectronic receiver
    46.
    发明授权
    Differential charge and dump optoelectronic receiver 失效
    差分充放电光电接收器

    公开(公告)号：US6091531A

    公开(公告)日：2000-07-18

    申请号：US15897

    申请日：1998-01-30

    申请人： Daniel B. Schwartz ,  Christopher K. Y. Chun ,  Stephen G. Shook

    发明人： Daniel B. Schwartz ,  Christopher K. Y. Chun ,  Stephen G. Shook

    IPC分类号： H04B10/69 ,  H04B10/06

    CPC分类号： H04B10/695 ,  H04B10/6932

    摘要： A differential charge and dump optoelectronic receiver for baseband digital optoelectronic data links is disclosed having a preamplifier and a voltage controlled current source that defines the tail current of a differential pair functioning as a two quadrant multiplier, and using capacitors as loads on the differential pair making said differential pair an integrator. The integrator provides a full differential output, part of which is fedback to control the gain of the preamplifier. In a preferred embodiment, one integrator pair is used to recover the data from a Manchester encoded data stream. In another preferred embodiment, two pairs of integrators are used for QPSK like codes.

    摘要翻译： 公开了一种用于基带数字光电数据链路的差分充电和转储光电接收器，其具有前置放大器和电压控制电流源，其限定用作二象限乘法器的差分对的尾电流，并且使用电容器作为差分对上的负载 所述差分对是积分器。 积分器提供全差分输出，其中一部分反馈控制前置放大器的增益。 在优选实施例中，使用一个积分器对来从曼彻斯特编码数据流中恢复数据。 在另一个优选实施例中，两对积分器被用于QPSK相似代码。

    Non-linear burst mode data receiver
    49.
    发明授权
    Non-linear burst mode data receiver 失效
    非线性突发模式数据接收器

    公开(公告)号：US5394108A

    公开(公告)日：1995-02-28

    申请号：US937034

    申请日：1992-08-31

    申请人： Christopher K. Y. Chun ,  Ray D. Sundstrom

    发明人： Christopher K. Y. Chun ,  Ray D. Sundstrom

    IPC分类号： H04L25/02 ,  H03K3/287 ,  H04B10/158 ,  G06G7/18

    CPC分类号： H04B10/6931 ,  H03K3/287

    摘要： Binary current signals are differentiated to produce pulses indicative of the front and rear edges. The pulses are amplified and utilized in a latch to regenerate binary voltage signals which are amplified replicas of the input signals. Because of the input differentiator the sensitivity of the circuit remains high while the latched output makes the circuit burst mode ready.

    摘要翻译： 二进制电流信号被微分以产生指示前边缘和后边缘的脉冲。 脉冲被放大并用于锁存器中以再生二进制电压信号，这是输入信号的放大副本。 由于输入微分器，电路的灵敏度保持高电平，而锁存的输出使电路突发模式准备就绪。

    Optical interface unit and method of making
    50.
    发明授权
    Optical interface unit and method of making 失效
    光接口单元及其制作方法

    公开(公告)号：US5384873A

    公开(公告)日：1995-01-24

    申请号：US131175

    申请日：1993-10-04

    申请人： Christopher K. Y. Chun ,  Shun-Meen Kuo

    发明人： Christopher K. Y. Chun ,  Shun-Meen Kuo

    IPC分类号： G02B6/42 ,  G02B6/28

    CPC分类号： G02B6/4292 ,  G02B6/4214 ,  G02B6/4249

    摘要： A plurality of electrical traces and a light emitting device having a working portion is disposed on an interconnect substrate. A first optical portion having a first surface, a second surface, and a tapered surface is disposed onto the interconnect substrate. The first surface of the optical portion covers the working portion of the light emitting device, a second surface of the first optical portion is positioned parallel to the working portion of the light emitting device, and the tapered surface extends from the second surface toward the working portion of the light emitting device for guiding light emitted from the working portion of the light emitting device to the second surface.

    摘要翻译： 多个电迹线和具有工作部分的发光器件设置在互连衬底上。 具有第一表面，第二表面和锥形表面的第一光学部分设置在互连基板上。 光学部分的第一表面覆盖发光器件的工作部分，第一光学部分的第二表面平行于发光器件的工作部分定位，锥形表面从第二表面延伸到工作 用于将从发光装置的工作部分发射的光引导到第二表面的发光装置的一部分。