公开(公告)号：US20180366434A1

公开(公告)日：2018-12-20

申请号：US15625676

申请日：2017-06-16

Applicant: Micron Technology, Inc.

Inventor： Benjamin L. McClain ,  Brandon P. Wirz ,  Zhaohui Ma

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: A bond tip for thermocompression bonding a bottom surface includes a die contact area and a low surface energy material covering at least a portion of the bottom surface. The low surface energy material may cover substantially all of the bottom surface, or only a peripheral portion surrounding the die contact area. The die contact area may be recessed with respect to the peripheral portion a depth at least as great as a thickness of a semiconductor die to be received in the recessed die contact area. A method of thermocompression bonding is also disclosed.

公开(公告)号：US20180342475A1

公开(公告)日：2018-11-29

申请号：US15603175

申请日：2017-05-23

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  David R. Hembree

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L25/18

Abstract: A semiconductor device assembly is provided. The assembly includes a first semiconductor die and a second semiconductor die disposed over the first semiconductor die. The assembly further includes a plurality of die support structures between the first and second semiconductor dies and a plurality of interconnects between the first and second semiconductor dies. Each of the plurality of die support structures includes a stand-off pillar and a stand-off pad having a first bond material with a first solder joint thickness between them. Each of the plurality of interconnects includes a conductive pillar and a conductive pad having a second bond material with a second solder joint thickness between them. The first solder joint thickness is less than the second solder joint thickness.

公开(公告)号：US10043688B1

公开(公告)日：2018-08-07

申请号：US15867071

申请日：2018-01-10

Applicant: Micron Technology, Inc.

Inventor： Jeremy E. Minnich ,  Brandon P. Wirz ,  Bret K. Street ,  James M. Derderian

IPC: B32B43/00 ,  H01L21/67 ,  H01L21/683

Abstract: An apparatus, system, and a method of using the apparatus or system that includes a bladder positioned between tape and an adhesive layer configured to selectively connect the tape to a semiconductor device. The bladder includes one or more chambers that may be selectively expanded to move a portion of the bladder and adhesive layer away from the tape, which may enable the removal of the semiconductor device. The flow of fluid into each of the chambers may selectively expand the chambers. The chambers may have a substantially rounded upper profile or a substantially pointed upper profile. A material within the chambers may be heated to expand the chambers. A plurality of conduits may permit the flow of fluid into the chambers. The conduits may be inserted into the bladder. The chambers may be collapsed after expansion to enable the removal of a semiconductor device from the tape.

公开(公告)号：US20170287857A1

公开(公告)日：2017-10-05

申请号：US15624493

申请日：2017-06-15

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Jaspreet S. Gandhi ,  Christopher J. Gambee ,  Satish Yeldandi

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03614 ,  H01L2224/038 ,  H01L2224/0382 ,  H01L2224/039 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05583 ,  H01L2224/05584 ,  H01L2224/05687 ,  H01L2224/94 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/365 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/053 ,  H01L2924/054 ,  H01L2224/03

Abstract: The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects or other types of interconnects. In one embodiment, a method for forming under-bump metal (UBM) structures on a semiconductor die comprises constructing a UBM pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material. The first material has first electrical potential and the second material has a second electrical potential greater than the first electrical potential. The method further comprises reducing the difference in the electrical potential between the first material and the second material, and then removing second areas of the seed structure between the UBM pillars thereby forming UBM structures on the semiconductor die.

公开(公告)号：US20250132279A1

公开(公告)日：2025-04-24

申请号：US18790320

申请日：2024-07-31

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Andrew M. Bayless ,  Owen R. Fay

IPC: H01L23/00

Abstract: A semiconductor device is presented. The semiconductor device includes a lower semiconductor die, a stack of upper semiconductor dies disposed over the lower semiconductor die, a non-conductive film material disposed between adjacent semiconductor dies of the lower semiconductor die and the stack of upper semiconductor dies, and an epoxy material disposed on at least one sidewall of the stack of upper semiconductor dies, wherein the epoxy material has a different material composition to the NCF material.

公开(公告)号：US20250015000A1

公开(公告)日：2025-01-09

申请号：US18893435

申请日：2024-09-23

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Andrew M. Bayless

IPC: H01L23/532 ,  H01L21/78 ,  H01L23/31 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065

Abstract: Semiconductor dies with edges protected and methods for generating the semiconductor dies are disclosed. Further, the disclosed methods provide for separating the semiconductor dies without using a dicing technique. In one embodiment, trenches are formed on a front side of a substrate including semiconductor dies. Individual trenches correspond to scribe lines of the substrate where each trench has a depth greater than a final thickness of the semiconductor dies. A composite layer may be formed on sidewalls of the trenches to protect the edges of the semiconductor dies. The composite layer includes a metallic layer that shields the semiconductor dies from electromagnetic interference. Subsequently, the substrate may be thinned from a back side to singulate individual semiconductor dies from the substrate.

公开(公告)号：US20240429191A1

公开(公告)日：2024-12-26

申请号：US18827462

申请日：2024-09-06

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Benjamin L. McClain

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18

Abstract: A semiconductor device assembly is provided. The assembly includes a first package element and a second package element disposed over the first package element. The assembly further includes a plurality of die support structures between the first and second package elements, wherein each of the plurality of die support structures has a first height, a lower portion surface-mounted to the first package element and an upper portion in contact with the second package element. The assembly further includes a plurality of interconnects between the first and second package elements, wherein each of the plurality of interconnects includes a conductive pillar having a second height, a conductive pad, and a bond material with a solder joint thickness between the conductive pillar and the conductive pad. The first height is about equal to a sum of the solder joint thickness and the second height.

公开(公告)号：US20240266191A1

公开(公告)日：2024-08-08

申请号：US18620993

申请日：2024-03-28

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Liang Chun Chen

IPC: H01L21/56 ,  H01L21/48

CPC classification number: H01L21/56 ,  H01L21/4875 ,  H01L21/4878

Abstract: Encapsulation warpage reduction for semiconductor die assemblies, and associated methods and systems are disclosed. In one embodiment, a semiconductor die assembly includes an interface die, a stack of semiconductor dies attached to a surface of the interface die, where the stack of semiconductor dies has a first height from the surface. The semiconductor die assembly also includes an encapsulant over the surface and surrounding the stack of semiconductor dies, where the encapsulant includes a sidewall with a first portion extending from the surface to a second height less than the first height and a second portion extending from the second height to the first height. Further, the first portion has a first texture and the second portion has a second texture different from the first texture.

公开(公告)号：US11911904B2

公开(公告)日：2024-02-27

申请号：US16930144

申请日：2020-07-15

Applicant: Micron Technology, Inc.

Inventor： Kuan Wei Tseng ,  Brandon P. Wirz

IPC: B25J9/16 ,  B25J19/02 ,  H05K13/08 ,  B25J13/08 ,  H01L23/00 ,  H01L21/67

CPC classification number: B25J9/1633 ,  B25J13/085 ,  B25J19/028 ,  H01L21/67144 ,  H01L24/75 ,  H05K13/082 ,  H01L2224/7565 ,  H01L2224/7592

Abstract: An apparatus for handling microelectronic devices comprises a pick arm having a pick surface configured for receiving a microelectronic device thereon, drives for moving the pick arm and reorienting the pick surface in the X, Y and Z planes and about a horizontal rotational axis and a vertical rotational axis, and a sensor device carried by the pick arm and configured to detect at least one of at least one magnitude of force and at least one location of force applied between the pick surface and a structure contacted by the pick surface or a structure and a microelectronic device carried on the pick surface.

公开(公告)号：US20230420300A1

公开(公告)日：2023-12-28

申请号：US18243664

申请日：2023-09-08

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Brandon P. Wirz

IPC: H01L21/78 ,  H01L21/50 ,  H01L21/683 ,  H01L21/67

CPC classification number: H01L21/78 ,  H01L21/50 ,  H01L21/6836 ,  H01L21/67051 ,  H01L2221/68322 ,  H01L2221/68327 ,  H01L21/6708

Abstract: Methods for releasing thinned semiconductor dies from a mount tape and associated apparatuses are disclosed. In one embodiment, a sacrificial layer may be disposed at a back side of thinned substrate including semiconductor dies. The sacrificial layer includes materials soluble in contact with a fluid (and/or vapor). A sheet of perforated mount tape may be attached to the sacrificial layer and an ejection component may be provided under a target semiconductor die to be released. The ejection component is configured to create a locally confined puddle of the fluid under the target semiconductor die such that the sacrificial layer is removed to release the target semiconductor die from the mount tape. Further, a support component may be provided to pick up the target semiconductor die after the target semiconductor die is released from the mount tape.