公开(公告)号：US20180047432A1

公开(公告)日：2018-02-15

申请号：US15233821

申请日：2016-08-10

Applicant: Micron Technology, Inc.

Inventor： Chikara Kondo ,  Chiaki Dono

IPC: G11C7/10 ,  G06F13/42

CPC classification number: G11C7/1006 ,  G06F13/4282 ,  G11C5/025 ,  G11C5/066 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  Y02D10/14 ,  Y02D10/151

Abstract: Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first semiconductor chip and a second semiconductor chips that are stacked with each other via through substrate vias (TSVs) provided in one of the first semiconductor chip and the second semiconductor chip. The first semiconductor chip and the second semiconductor chips communicate with each other by use of data bus inversion data that have been encoded using a DBI algorithm.

公开(公告)号：US09881693B2

公开(公告)日：2018-01-30

申请号：US15045061

申请日：2016-02-16

Applicant: Micron Technology, Inc.

Inventor： Chikara Kondo ,  Tomoyuki Shibata ,  Ryota Suzuki

IPC: G11C29/00 ,  G11C29/12 ,  G11C29/44 ,  G11C29/56

CPC classification number: G11C29/1201 ,  G11C11/417 ,  G11C29/12015 ,  G11C29/4401 ,  G11C29/48 ,  G11C2029/5602

Abstract: Apparatuses including an interface chip that interfaces with dice through memory channels are described. An example apparatus includes: an interface chip that interfaces with a plurality of dice through a plurality of memory channels, each of the dice comprising a plurality of memory cells, and the interface chip comprising a test circuit. The test circuit includes: first and second terminals corresponding to the first and second memory channels respectively; a test terminal and a built in self test (BIST) circuit common to the first and second memory channels; and a selector coupled to the first and second terminals, the test terminal and the BIST circuit, and couples a first selected one of the first terminal, the test terminal and the BIST circuit to the first channel and a second selected one of the second terminal, the test terminal and the BIST circuit to the second channel.

公开(公告)号：US20230351063A1

公开(公告)日：2023-11-02

申请号：US18333406

申请日：2023-06-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chikara Kondo ,  Kazuhiro Kurihara

IPC: G06F21/85 ,  G06F21/79 ,  G11C29/12 ,  G06F12/14 ,  G06F21/60

CPC classification number: G06F21/85 ,  G06F21/79 ,  G11C29/1201 ,  G06F12/1408 ,  G06F21/602

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for signal encryption in high bandwidth memory. A high bandwidth memory (HBM) may include a mix of secure circuits and non-secure circuits, which are coupled to secure and non-secure registers respectively. Information may be communicated between the secure and non-secure registers along an interface. The information associated with the secure register may be encrypted. When information is written to the secure register, an encryption circuit in the HBM may first decrypt the information before it is written to the secure register. When information is read from the secure register, it may first be encrypted by the encryption circuit before it is provided along the interface.

公开(公告)号：US11581056B2

公开(公告)日：2023-02-14

申请号：US17124169

申请日：2020-12-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chiaki Dono ,  Chikara Kondo ,  Roman A. Royer

IPC: G11C29/44 ,  G11C29/48 ,  G11C29/30 ,  G11C29/36 ,  G11C29/12

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for direct access hybrid testing. A memory device, such as a high bandwidth memory (HBM) may include direct access terminals. During a testing procedure, test instructions may be provided to the memory through the direct access terminals. The test instructions include a data pointer which is associated with one of a plurality of test patterns pre-loaded in the memory and an address. The selected test pattern may be written to, and subsequently read from, the memory cells associated with the address. The read test pattern may be compared to the selected test pattern to generate result information. The test patterns may be loaded to the memory, and the result information may be read out from the memory, in an operational mode different than the operational mode in which the test instructions are provided.

公开(公告)号：US20210390999A1

公开(公告)日：2021-12-16

申请号：US17446569

申请日：2021-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshihito Morishita ,  Chikara Kondo

IPC: G11C11/4078 ,  G11C29/02 ,  H04L9/06 ,  G11C11/408

Abstract: Apparatuses, systems, and methods for fuse based device identification. A device may include a number of fuses which are used to encode permanent information on the device. The device may receive an identification request, and may generate an identification number based on the states of at least a portion of the fuses. For example, the device may include a hash generator, which may generate the identification number by using the fuse information as a seed for a hash algorithm.

公开(公告)号：US10714206B2

公开(公告)日：2020-07-14

申请号：US15833425

申请日：2017-12-06

Applicant: Micron Technology, Inc.

Inventor： Chikara Kondo ,  Tomoyuki Shibata ,  Ryota Suzuki

IPC: G11C29/00 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/56 ,  G11C11/417

Abstract: Apparatuses including an interface chip that interfaces with dice through memory channels are described. An example apparatus includes: an interface chip that interfaces with a plurality of dice through a plurality of memory channels, each of the dice comprising a plurality of memory cells, and the interface chip comprising a test circuit. The test circuit includes: first and second terminals corresponding to the first and second memory channels respectively; a test terminal and a built in self test (BIST) circuit common to the first and second memory channels; and a selector coupled to the first and second terminals, the test terminal and the BIST circuit, and couples a first selected one of the first terminal, the test terminal and the BIST circuit to the first channel and a second selected one of the second terminal, the test terminal and the BIST circuit to the second channel.

公开(公告)号：US10553263B2

公开(公告)日：2020-02-04

申请号：US16225303

申请日：2018-12-19

Applicant: Micron Technology, Inc.

Inventor： Chikara Kondo ,  Tomoyuki Shibata ,  Chiaki Dono ,  Seiji Narui ,  Minehiko Uehara ,  Taihei Shido ,  Homare Sato

IPC: G11C7/22 ,  G11C16/32 ,  G11C19/28 ,  G11C7/10

Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described. An example apparatus includes: a first chip, wherein the first chip includes a receiver that receives a data strobe signal and further generates an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal including a first edge and a second edge following the first edge; a buffer circuit coupled to a set of input terminals and captures first data at the set of input terminals responsive, at least in part, to the first edge of the internal strobe signal and further captures second data at the set of input terminals responsive, at least in part, to the second edge of the internal strobe signal; a driver coupled between the buffer circuit and a set of data terminals and configured to be activated to provide the first and second data from the buffer circuit to the set of data terminals responsive, at least in part, to a control signal; and a width expanding circuit that provides the control signal responsive, at least in part, to the internal strobe signal.

公开(公告)号：US10395748B2

公开(公告)日：2019-08-27

申请号：US15183654

申请日：2016-06-15

Applicant: Micron Technology, Inc.

Inventor： Tomoyuki Shibata ,  Chikara Kondo ,  Hiroyuki Tanaka

IPC: G11C29/38 ,  G11C29/44 ,  G11C29/00 ,  G11C29/12 ,  G11C29/14 ,  G11C29/36 ,  G11C29/42 ,  G11C29/48 ,  G11C5/02 ,  G11C29/04

Abstract: Apparatuses and methods of sharing error correction memory on an interface chip are described. An example apparatus includes: at least one memory chip having a plurality of first memory cells and an interface chip coupled to the at least one memory chip and having a control circuit and a storage area. The control circuit detects one or more defective memory cells of the first memory cells of the at least one memory chip. The control circuit further stores first defective address information of the one or more defective memory cells of the first memory cells into the storage area. The interface chip responds to the first defective address information and an access request to access the storage area in place of the at least one memory chip when the access request has been provided with respect to the one or more defective memory cells of the first memory cells.

公开(公告)号：US20190115057A1

公开(公告)日：2019-04-18

申请号：US15783606

申请日：2017-10-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Homare Sato ,  Chiaki Dono ,  Chikara Kondo

IPC: G11C7/22 ,  H03K3/037

Abstract: Apparatuses and methods for providing multiphase clock signals are described. An example apparatus includes first, second, third and fourth clocked inverters, first and second clock terminals, and first and second latch circuits. An input node and an output node of the first clocked inverter is coupled respectively to an output node of the fourth clocked inverter and an input node of the second clocked inverter. An input node and an output node of the third clocked inverter is coupled to an output node of the second clocked inverter and an input node of the fourth clocked inverter. The first and second dock terminals are supplied respectively with first and second clock signals. The first latch is coupled between the output nodes of the first and third clocked inverters, and the second latch circuit is coupled between the output nodes of the second and fourth clocked inverters.

公开(公告)号：US10262704B1

公开(公告)日：2019-04-16

申请号：US15783606

申请日：2017-10-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Homare Sato ,  Chiaki Dono ,  Chikara Kondo

IPC: G11C8/00 ,  G11C7/22 ,  H03K3/037

Abstract: Apparatuses and methods for providing multiphase clock signals are described. An example apparatus includes first, second, third and fourth clocked inverters, first and second clock terminals, and first and second latch circuits. An input node and an output node of the first clocked inverter is coupled respectively to an output node of the fourth clocked inverter and an input node of the second clocked inverter. An input node and an output node of the third clocked inverter is coupled to an output node of the second clocked inverter and an input node of the fourth clocked inverter. The first and second clock terminals are supplied respectively with first and second clock signals. The first latch is coupled between the output nodes of the first and third clocked inverters, and the second latch circuit is coupled between the output nodes of the second and fourth clocked inverters.