公开(公告)号：US11569255B2

公开(公告)日：2023-01-31

申请号：US17314384

申请日：2021-05-07

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson ,  Ugo Russo

IPC: H01L27/1157 ,  H01L21/28 ,  H01L27/11582 ,  H01L29/423 ,  H01L29/51

Abstract: Electronic apparatus and methods of forming the electronic apparatus may include one or more charge trap structures for use in a variety of electronic systems and devices, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, a void is located between the charge trap region and a region on which the charge trap structure is disposed. In various embodiments, a tunnel region separating a charge trap region from a semiconductor pillar of a charge trap structure, can be arranged such that the tunnel region and the semiconductor pillar are boundaries of a void. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US11205660B2

公开(公告)日：2021-12-21

申请号：US16705388

申请日：2019-12-06

Applicant: Micron Technology, Inc.

Inventor： Manzar Siddik ,  Chris M. Carlson ,  Terry H. Kim ,  Kunal Shrotri ,  Srinath Venkatesan

IPC: H01L27/11582 ,  H01L21/3215 ,  H01L21/3115 ,  H01L27/11556

Abstract: A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. The strings of memory cells in the stack comprise channel-material strings and storage-material strings extending through the insulative tiers and the conductive tiers. At least some of the storage material of the storage-material strings in individual of the insulative tiers are intrinsically less charge-transmissive than is the storage material in the storage-material strings in individual of the conductive tiers. Other aspects, including method, are disclosed.

公开(公告)号：US20210265365A1

公开(公告)日：2021-08-26

申请号：US17314384

申请日：2021-05-07

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson ,  Ugo Russo

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L29/51 ,  H01L29/423 ,  H01L21/28

Abstract: Electronic apparatus and methods of forming the electronic apparatus may include one or more charge trap structures for use in a variety of electronic systems and devices, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, a void is located between the charge trap region and a region on which the charge trap structure is disposed. In various embodiments, a tunnel region separating a charge trap region from a semiconductor pillar of a charge trap structure, can be arranged such that the tunnel region and the semiconductor pillar are boundaries of a void. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20210151454A1

公开(公告)日：2021-05-20

申请号：US17160956

申请日：2021-01-28

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Chris M. Carlson ,  Collin Howder

IPC: H01L27/11556 ,  G11C8/14 ,  G11C16/04 ,  G06F3/06 ,  H01L27/11582 ,  H01L27/11529 ,  H01L27/11558 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11524

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. First charge-blocking material is formed to extend elevationally along the vertically-alternating tiers. The first charge-blocking material has k of at least 7.0 and comprises a metal oxide. A second charge-blocking material is formed laterally inward of the first charge-blocking material. The second charge-blocking material has k less than 7.0. Storage material is formed laterally inward of the second charge-blocking material. Insulative charge-passage material is formed laterally inward of the storage material. Channel material is formed to extend elevationally along the insulative tiers and the wordline tiers laterally inward of the insulative charge-passage material. Structure embodiments are disclosed.

公开(公告)号：US20200258906A1

公开(公告)日：2020-08-13

申请号：US16856976

申请日：2020-04-23

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson

IPC: H01L27/11582 ,  H01L21/28 ,  H01L29/423

Abstract: Various embodiments, disclosed herein, include methods and apparatus having charge trap structures, where each charge trap structure includes a dielectric harrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, material of the dielectric harrier of each of the charge trap structures may have a dielectric constant greater than that of aluminum oxide. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US10446574B2

公开(公告)日：2019-10-15

申请号：US15975902

申请日：2018-05-10

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/28 ,  G11C16/04 ,  G11C16/16

Abstract: A memory cell comprises, in the following order, channel material, a charge-passage structure, charge-storage material, a charge-blocking region, and a control gate. The charge-passage structure comprises a first material closest to the channel material, a third material furthest from the channel material, and a second material between the first material and the third material. Dielectric constant (k) of the first material is less than 5.0. Sum of bandgap (BG) and electron affinity (chi) of the second material is no greater than 6.7 eV. The k of the second material is at least 5.0. Sum of BG and chi of the third material is less than 9.0 eV and at least 0.5 eV greater than the sum of the BG and the chi of the second material.

公开(公告)号：US10388667B2

公开(公告)日：2019-08-20

申请号：US16102987

申请日：2018-08-14

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson ,  M. Jared Barclay

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/51 ,  H01L29/792 ,  H01L21/28

Abstract: Some embodiments include a memory cell which has, in the following order; a control gate, charge-blocking material, charge-trapping material, a first oxide, a charge-passage structure, a second oxide, and channel material. The charge-passage structure has a central region sandwiched between first and second regions. The central region has a lower probability of trapping charges and/or a lower rate of trapping charges than the first and second regions. Some embodiments include an integrated structure having a vertical stack of alternating conductive levels and insulative levels, and having a charge-passage structure extending vertically along the vertical stack. Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and wordline levels, and having a charge-passage structure extending vertically along the vertical stack.

公开(公告)号：US20190013404A1

公开(公告)日：2019-01-10

申请号：US15645202

申请日：2017-07-10

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson ,  Hung-Wei Liu ,  Jie Li ,  Dimitrios Pavlopoulos

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/20 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/02 ,  H01L29/788 ,  H01L29/792

Abstract: Some embodiments include device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen-containing material directly against the semiconductor channel material and on an opposing side of the semiconductor channel material from the dielectric region. Some embodiments include a device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen within at least some of the semiconductor channel material. Some embodiments include a NAND memory array which includes a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. Charge-storage material is between the channel material and the wordline levels. Dielectric material is between the channel material and the charge-storage material. Nitrogen is within the channel material. Some embodiments include methods of forming NAND memory arrays.

公开(公告)号：US10008381B2

公开(公告)日：2018-06-26

申请号：US14929070

申请日：2015-10-30

Applicant: Micron Technology, Inc.

Inventor： Nik Mirin ,  Tsai-Yu Huang ,  Vishwanath Bhat ,  Chris M. Carlson ,  Vassil N. Antonov

IPC: H01L21/02 ,  C23C16/40 ,  C23C16/455 ,  H01G4/08 ,  H01G4/12 ,  H01G4/33 ,  H01L27/108 ,  H01L49/02 ,  C01G23/04 ,  H01L23/373 ,  H05K1/02 ,  H01L21/285 ,  H01L21/3205 ,  H01L23/367

CPC classification number: H01L21/02186 ,  C01G23/04 ,  C23C16/405 ,  C23C16/45534 ,  H01G4/085 ,  H01G4/1227 ,  H01G4/33 ,  H01L21/02233 ,  H01L21/02244 ,  H01L21/28556 ,  H01L21/32051 ,  H01L23/367 ,  H01L23/3735 ,  H01L23/3736 ,  H01L27/10808 ,  H01L27/1085 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H05K1/0203 ,  Y02P20/129 ,  Y10T428/24802 ,  Y10T428/24975 ,  H01L2924/00

Abstract: Some embodiments include methods of forming rutile-type titanium oxide. A monolayer of titanium nitride may be formed. The monolayer of titanium nitride may then be oxidized at a temperature less than or equal to about 550° C. to convert it into a monolayer of rutile-type titanium oxide. Some embodiments include methods of forming capacitors that have rutile-type titanium oxide dielectric, and that have at least one electrode comprising titanium nitride. Some embodiments include thermally conductive stacks that contain titanium nitride and rutile-type titanium oxide, and some embodiments include methods of forming such stacks.

公开(公告)号：US09499907B2

公开(公告)日：2016-11-22

申请号：US13926289

申请日：2013-06-25

Applicant: Micron Technology, Inc.

Inventor： Zhe Song ,  Chris M. Carlson

IPC: C23C16/455 ,  C23C16/44 ,  C23C16/40 ,  H01G4/08 ,  H01G4/12 ,  H01G4/33 ,  H01L21/02 ,  H01L49/02

CPC classification number: C23C16/45553 ,  C23C16/405 ,  C23C16/45527 ,  H01G4/085 ,  H01G4/12 ,  H01G4/33 ,  H01L21/02159 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L28/40

Abstract: A method of forming a material over a substrate includes performing at least one iteration of the following temporally separated ALD-type sequence. First, an outermost surface of a substrate is contacted with a first precursor to chemisorb a first species onto the outermost surface from the first precursor. Second, the outermost surface is contacted with a second precursor to chemisorb a second species different from the first species onto the outermost surface from the second precursor. The first and second precursors include ligands and different central atoms. At least one of the first and second precursors includes at least two different composition ligands. The two different composition ligands are polyatomic or a lone halogen. Third, the chemisorbed first species and the chemisorbed second species are contacted with a reactant which reacts with the first species and with the second species to form a reaction product new outermost surface of the substrate.