公开(公告)号：US20190244908A1

公开(公告)日：2019-08-08

申请号：US15887064

申请日：2018-02-02

Applicant: Micron Technology, Inc.

Inventor： Christopher W. Petz ,  Everett A. McTeer

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/285 ,  H01L23/528 ,  H01L21/311

CPC classification number: H01L23/53209 ,  H01L21/2855 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/76834 ,  H01L21/76852 ,  H01L23/528 ,  H01L23/5329

Abstract: Some embodiments include an integrated structure having a conductive region which contains one or more elements from Group 2 of the periodic table. Some embodiments include an integrated structure which has a conductive region over and directly against a base material. The conductive region includes one or more elements from Group 2 of the periodic table, and has a pair of opposing sidewalls along a cross-section. A capping material is over and directly against the conductive region. Protective material is along and directly against the sidewalls of the protective region.

公开(公告)号：US10325653B2

公开(公告)日：2019-06-18

申请号：US15856806

申请日：2017-12-28

Applicant: Micron Technology, Inc.

Inventor： Yongjun Jeff Hu ,  Tsz W. Chan ,  Christopher W. Petz ,  Everett Allen McTeer

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming a memory stack out of a plurality of elements. A sidewall liner is formed on a sidewall of the memory stack using a physical vapor deposition (PVD) process, including an adhesion species and a dielectric, such that the adhesion species intermixes with an element of the memory stack to terminate unsatisfied atomic bonds of the element and the dielectric forms a dielectric film with the adhesive species on the sidewall.

公开(公告)号：US20180144795A1

公开(公告)日：2018-05-24

申请号：US15856806

申请日：2017-12-28

Applicant: Micron Technology, Inc.

Inventor： Yongjun Jeff Hu ,  Tsz W. Chan ,  Christopher W. Petz ,  Everett Allen McTeer

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/0004 ,  G11C2213/35 ,  G11C2213/52 ,  G11C2213/71 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1675

Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming a memory stack out of a plurality of elements. A sidewall liner is formed on a sidewall of the memory stack using a physical vapor deposition (PVD) process, including an adhesion species and a dielectric, such that the adhesion species intermixes with an element of the memory stack to terminate unsatisfied atomic bonds of the element and the dielectric forms a dielectric film with the adhesive species on the sidewall.

公开(公告)号：US09431606B1

公开(公告)日：2016-08-30

申请号：US14825087

申请日：2015-08-12

Applicant: Micron Technology, Inc.

Inventor： Durai Vishak Nirmal Ramaswamy ,  Dale W. Collins ,  Christopher W. Petz ,  Beth R. Cook

IPC: H01L45/00

CPC classification number: H01L45/1266 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/14

Abstract: Some embodiments include a memory cell having a pair of electrodes, and a plurality of switching levels between the electrodes. Each switching level has an ion buffer region and a dielectric region. At least one switching level differs from another switching level in one or both of thickness and composition of the ion buffer region and/or the dielectric region.

Abstract translation: 一些实施例包括具有一对电极的存储单元和电极之间的多个开关电平。 每个开关电平具有离子缓冲区和电介质区。 至少一个开关电平与离子缓冲区域和/或电介质区域的厚度和组成中的一个或两个中的另一个开关电平不同。

公开(公告)号：US20240038588A1

公开(公告)日：2024-02-01

申请号：US17815359

申请日：2022-07-27

Applicant: Micron Technology, Inc.

Inventor： Terrence B. McDaniel ,  Vinay Nair ,  Russell A. Benson ,  Christopher W. Petz ,  Si-Woo Lee ,  Silvia Borsari ,  Ping Chieh Chiang ,  Luca Fumagalli

IPC: H01L21/768 ,  H01L27/108

CPC classification number: H01L21/76897 ,  H01L27/10855 ,  H01L27/10885

Abstract: A method of forming a microelectronic device comprises forming interlayer dielectric material over a base structure comprising semiconductive structures separated from one another by insulative structures. Sacrificial line structures separated from one another by trenches are formed over the interlayer dielectric material. The sacrificial line structures horizontally overlap some of the semiconductive structures, and the trenches horizontally overlap some other of the semiconductive structures. Plug structures are formed within horizontal areas of the trenches and extend through the interlayer dielectric material and into the some other of the semiconductive structures. The sacrificial line structures are replaced with additional trenches. Conductive contact structures are formed within horizontal areas of the additional trenches and extend through the interlayer dielectric material and into the some of the semiconductive structures. Conductive line structures are formed within the additional trenches and in contact with the conductive contact structures.

公开(公告)号：US11527548B2

公开(公告)日：2022-12-13

申请号：US16216088

申请日：2018-12-11

Applicant: Micron Technology, Inc.

Inventor： Haoyu Li ,  Everett A. McTeer ,  Christopher W. Petz ,  Yongjun J. Hu

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/311 ,  H01L27/11524 ,  H01L21/28

Abstract: A semiconductor device comprises a semiconductor material extending through a stack of alternating levels of a conductive material and an insulative material, and a material comprising cerium oxide and at least another oxide adjacent to the semiconductor material. Related electronic systems and methods are also disclosed.

公开(公告)号：US20220302032A1

公开(公告)日：2022-09-22

申请号：US17806438

申请日：2022-06-10

Applicant: Micron Technology Inc.

Inventor： Jordan D. Greenlee ,  Christian George Emor ,  Luca Fumagalli ,  John D. Hopkins ,  Rita J. Klein ,  Christopher W. Petz ,  Everett A. McTeer

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: A microelectronic device includes a first conductive structure, a barrier structure, a conductive liner structure, and a second conductive structure. The first conductive structure is within a first filled opening in a first dielectric structure. The barrier structure is within the first filled opening in the first dielectric structure and vertically overlies the first conductive structure. The conductive liner structure is on the barrier structure and is within a second filled opening in a second dielectric structure vertically overlying the first dielectric structure. The second conductive structure vertically overlies and is horizontally surrounded by the conductive liner structure within the second filled opening in the second dielectric structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US10991882B2

公开(公告)日：2021-04-27

申请号：US16552745

申请日：2019-08-27

Applicant: Micron Technology, Inc.

Inventor： Christopher W. Petz ,  Yongjun Jeff Hu ,  Scott E. Sills ,  D. V. Nirmal Ramaswamy

IPC: H01L23/52 ,  G11C13/00 ,  H01L45/00 ,  H01L27/24 ,  H01L23/522 ,  H01L27/22 ,  C23C14/06 ,  C23C14/08 ,  C23C14/18 ,  C23C14/34 ,  C23C16/34 ,  C23C16/36 ,  C23C16/40 ,  C23C16/455

Abstract: A resistive memory element comprises a first electrode, an active material over the first electrode, a buffer material over the active material and comprising longitudinally extending, columnar grains of crystalline material, an ion reservoir material over the buffer material, and a second electrode over the ion reservoir material. A memory cell, a memory device, an electronic system, and a method of forming a resistive memory element are also described.

公开(公告)号：US10811419B1

公开(公告)日：2020-10-20

申请号：US16419730

申请日：2019-05-22

Applicant: Micron Technology, Inc.

Inventor： Devesh Dadhich Shreeram ,  Sanket S. Kelkar ,  Gurpreet S. Lugani ,  Paul A. Paduano ,  Matthew N. Rocklein ,  Sanjeev Sapra ,  Christopher W. Petz

IPC: H01L27/108 ,  H01L49/02

Abstract: Methods, apparatuses, and systems related to shaping a storage node material are described. An example method includes forming a pillar with a pattern of materials. The method further includes depositing a storage node material on a side of the pillar. The method further includes etching sacrificial materials within the pillar. The method further includes etching the storage node material in a direction from the pillar into the storage node.

公开(公告)号：US20200321340A1

公开(公告)日：2020-10-08

申请号：US16906718

申请日：2020-06-19

Applicant: Micron Technology, Inc.

Inventor： Kentaro Ishii ,  Yongjun J. Hu ,  Amirhasan Nourbakhsh ,  Durai Vishak Nirmal Ramaswamy ,  Christopher W. Petz ,  Luca Fumagalli

IPC: H01L27/108

Abstract: A method of forming an apparatus comprises forming a first metal nitride material over an upper surface of a conductive material within an opening extending through at least one dielectric material through a non-conformal deposition process. A second metal nitride material is formed over an upper surface of the first metal nitride material and side surfaces of the at least one dielectric material partially defining boundaries of the opening through a conformal deposition process. A conductive structure is formed over surfaces of the second metal nitride material within the opening. Apparatuses and electronic systems are also described.