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    Methods of combinatorial processing for screening multiple samples on a semiconductor substrate
    43.
    发明授权
    Methods of combinatorial processing for screening multiple samples on a semiconductor substrate 失效
    用于在半导体衬底上筛选多个样品的组合处理方法

    公开(公告)号：US08383430B2

    公开(公告)日：2013-02-26

    申请号：US13399719

    申请日：2012-02-17

    申请人： Guarav Verma ,  Tony P. Chiang ,  Imran Hashim ,  Sandra G Malhotra ,  Prashant B Phatak ,  Kurt H Weiner

    发明人： Guarav Verma ,  Tony P. Chiang ,  Imran Hashim ,  Sandra G Malhotra ,  Prashant B Phatak ,  Kurt H Weiner

    IPC分类号： H01L21/00

    CPC分类号： G01R31/2831 ,  G01R31/2834 ,  H01L22/34

    摘要： In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

    摘要翻译： 在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。 这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。 通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。 即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。 测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。

    Methods of Combinatorial Processing for Screening Multiple Samples on a Semiconductor Substrate
    45.
    发明申请
    Methods of Combinatorial Processing for Screening Multiple Samples on a Semiconductor Substrate 有权
    在半导体基板上筛选多个样品的组合处理方法

    公开(公告)号：US20100001269A1

    公开(公告)日：2010-01-07

    申请号：US12167118

    申请日：2008-07-02

    申请人： Gaurav Verma ,  Kurt Weiner ,  Prashant Phatak ,  Imran Hashim ,  Sandra Malhotra ,  Tony Chiang

    发明人： Gaurav Verma ,  Kurt Weiner ,  Prashant Phatak ,  Imran Hashim ,  Sandra Malhotra ,  Tony Chiang

    IPC分类号： C23C16/00 ,  H01L21/66 ,  H01L23/58

    CPC分类号： G01R31/2831 ,  G01R31/2834 ,  H01L22/34

    摘要： In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

    摘要翻译： 在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。 这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。 通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。 即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。 测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。

    Method of depositing a copper seed layer which promotes improved feature surface coverage
    46.
    发明授权
    Method of depositing a copper seed layer which promotes improved feature surface coverage 有权
    沉积铜种子层的方法，其促进改进的特征表面覆盖

    公开(公告)号：US06500762B2

    公开(公告)日：2002-12-31

    申请号：US10056751

    申请日：2002-01-24

    申请人： Imran Hashim ,  Hong-Mei Zhang ,  John C. Forster

    发明人： Imran Hashim ,  Hong-Mei Zhang ,  John C. Forster

    IPC分类号： H01L2144

    CPC分类号： H01L21/76877 ,  H01L21/2855 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： We have discovered a method of improving step coverage of a copper seed layer deposited over a semiconductor feature surface which is particularly useful for small size features having a high aspect ratio. We have demonstrated that it is possible to increase the copper seed layer coverage simultaneously at the bottom of a high aspect ratio contact via and on the walls of the via by increasing the percentage of the depositing copper species which are ions. The percentage of species ionization which is necessary to obtain sufficient step coverage for the copper seed layer is a function of the aspect ratio of the feature. An increase in the percentage of copper species which are ionized can be achieved using techniques known in the art, including but not limited to applicants' preferred technique, an inductively coupled RF ion metal plasma.

    摘要翻译： 我们已经发现了一种改进沉积在半导体特征表面上的铜籽晶层的台阶覆盖率的方法，该方法对于具有高纵横比的小尺寸特征特别有用。 我们已经证明，可以通过增加作为离子的沉积铜物质的百分比，在高纵横比接触通孔和通孔的壁上同时增加铜种子层覆盖。 获得铜种子层足够的阶梯覆盖所必需的物质电离的百分比是该特征的纵横比的函数。 可以使用本领域已知的技术来实现电离的铜物质的百分比的增加，包括但不限于申请人的优选技术，电感耦合RF离子金属等离子体。

    Copper alloy seed layer for copper metallization
    47.
    发明授权
    Copper alloy seed layer for copper metallization 失效
    铜合金种子层用于铜金属化

    公开(公告)号：US06387805B2

    公开(公告)日：2002-05-14

    申请号：US08878143

    申请日：1997-06-18

    申请人： Peijun Ding ,  Tony Chiang ,  Imran Hashim ,  Bingxi Sun ,  Barry Chin

    发明人： Peijun Ding ,  Tony Chiang ,  Imran Hashim ,  Bingxi Sun ,  Barry Chin

    IPC分类号： H01L2144

    CPC分类号： H01L21/76843 ,  C23C14/024 ,  C23C14/025 ,  C23C14/16 ,  C23C14/165 ,  C23C16/0281 ,  C23C16/06 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76867 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A copper metallization structure and its method of formation in which a layer of a copper alloy, such as Cu—Mg or Cu—Al is deposited over a silicon oxide based dielectric layer and a substantially pure copper layer is deposited over the copper alloy layer. The copper alloy layer serves as a seed or wetting layer for subsequent filling of via holes and trenches with substantially pure copper. Preferably, the copper alloy is deposited cold in a sputter process, but, during the deposition of the pure copper layer or afterwards in a separate annealing step, the temperature is raised sufficiently high to cause the alloying element of the copper alloy to migrate to the dielectric layer and form a barrier there against diffusion of copper into and through the dielectric layer. This barrier also promotes adhesion of the alloy layer to the dielectric layer, thereby forming a superior wetting and seed layer for subsequent copper full-fill techniques. Filling of the alloy-lined feature can be accomplished using PVD, CVD, or electro/electroless plating.

    摘要翻译： 在铜合金层上沉积铜基金属化结构及其形成方法，其中在氧化硅基介电层和基本上纯的铜层上沉积诸如Cu-Mg或Cu-Al的铜合金层。 铜合金层用作种子或润湿层，用于随后用基本上纯的铜填充通孔和沟槽。 优选地，铜合金在溅射过程中冷沉积，但是在纯铜层沉积期间或之后在单独的退火步骤中，温度升高到足够高以使铜合金的合金元素迁移到 电介质层，并形成阻挡铜，以扩散到介电层中并穿过介电层。 该屏障还促进了合金层对电介质层的粘附，从而形成了用于随后的铜全填充技术的优异的润湿和种子层。 可以使用PVD，CVD或电/无电镀来完成合金衬里特征的填充。

    Structure for improving low temperature copper reflow in semiconductor features
    48.
    发明授权
    Structure for improving low temperature copper reflow in semiconductor features 失效
    用于改善半导体特性中低温铜回流的结构

    公开(公告)号：US06352926B1

    公开(公告)日：2002-03-05

    申请号：US09709991

    申请日：2000-11-10

    申请人： Peijun Ding ,  Imran Hashim ,  Barry L. Chin

    发明人： Peijun Ding ,  Imran Hashim ,  Barry L. Chin

    IPC分类号： H01L2144

    CPC分类号： H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： We have discovered that complete copper filling of semiconductor features such as trenches and vias, without the formation of trapped voids, can be accomplished using a copper reflow process when the unfilled portion of the feature structure prior to reflow comprises a capillary within the feature, wherein the volume of the capillary represents between about 20% and about 90%, preferably between about 20% and about 75% of the original feature volume prior to filling with copper. The aspect ratio of the capillary is preferably at least 1.5. The maximum opening dimension of the capillary is less than about 0.8 &mgr;m. The preferred substrate temperature during the reflow process includes either a soak at an individual temperature or a temperature ramp-up or ramp-down where the substrate experiences a temperature within a range from about 300° C. to about 600° C., more preferably between about 300° C. and about 450° C. By controlling the percentage of the volume of the feature which is unfilled at the time of the reflow process and taking advantage of the surface tension and capillary action when the aspect ratio of the feature is at least 1.5, the copper fill material is easily pulled into the feature which comprises the capillary without the formation of voids along the walls of the feature. The preferred method of application of the last layer of copper prior to reflow (the layer of copper which produces the unfilled capillary within the feature) is electroplating, although CVD or evaporation or other conformal layer formation techniques may be used.

    摘要翻译： 我们已经发现，当回流焊之前的特征结构的未填充部分包括该特征内的毛细管时，可以使用铜回流工艺来实现半导体特征如沟槽和通孔的完全铜填充，例如沟槽和通孔，而不形成截留的空隙，其中 在填充铜之前，毛细管的体积代表原始特征体积的约20％至约90％，优选约20％至约75％。 毛细管的纵横比优选为1.5以上。 毛细管的最大开口尺寸小于约0.8μm。 在回流过程中优选的衬底温度包括在单独温度下浸泡或温度升高或斜坡下降，其中衬底经历温度在约300℃至约600℃的范围内，更优选地 在约300℃和约450℃之间。通过控制在回流工艺时未填充的特征的体积百分比，并且当特征的纵横比为 至少1.5，铜填充材料容易地被拉入包括毛细管的特征，而不沿着特征的壁形成空隙。 在回流之前施加最后一层铜的优选方法（在特征内产生未填充的毛细管的铜层）是电镀，尽管可以使用CVD或蒸发或其它共形层形成技术。

    Methods of combinatorial processing for screening multiple samples on a semiconductor substrate
    50.
    发明授权
    Methods of combinatorial processing for screening multiple samples on a semiconductor substrate 有权
    用于在半导体衬底上筛选多个样品的组合处理方法

    公开(公告)号：US08143619B2

    公开(公告)日：2012-03-27

    申请号：US12905945

    申请日：2010-10-15

    申请人： Gaurav Verma ,  Kurt Weiner ,  Prashant Phatak ,  Imran Hashim ,  Sandra Malhotra ,  Tony Chiang

    发明人： Gaurav Verma ,  Kurt Weiner ,  Prashant Phatak ,  Imran Hashim ,  Sandra Malhotra ,  Tony Chiang

    IPC分类号： H01L29/00

    CPC分类号： G01R31/2831 ,  G01R31/2834 ,  H01L22/34

    摘要： In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

    摘要翻译： 在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。 这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。 通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。 即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。 测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。