公开(公告)号：US06737724B2

公开(公告)日：2004-05-18

申请号：US10267689

申请日：2002-10-10

申请人： Katsuhiko Hieda ,  Kyoichi Suguro

发明人： Katsuhiko Hieda ,  Kyoichi Suguro

IPC分类号： H01L2900

CPC分类号： H01L29/517 ,  H01L21/28061 ,  H01L21/28079 ,  H01L21/28211 ,  H01L21/28238 ,  H01L21/324 ,  H01L29/495 ,  H01L29/51 ,  H01L29/513 ,  H01L29/518 ,  H01L29/665

摘要： Disclosed is a semiconductor device including a transistor structure including an epitaxial silicon layer formed on a main surface of an n-type semiconductor substrate, source-drain diffusion layers formed on at least the epitaxial silicon layer, a channel region formed between the source and drain regions, and a gate electrode formed on the channel region with a gate insulating film interposed therebetween, an element isolation region being sandwiched between adjacent transistor structures, wherein a punch-through stopper layer formed in a lower portion of the channel region has an impurity concentration higher than that of the channel region, and the source-drain diffusion layers do not extend to overlap with edge portion of insulating films for the element isolation.

摘要翻译： 公开了一种半导体器件，包括晶体管结构，该晶体管结构包括形成在n型半导体衬底的主表面上的外延硅层，至少形成在外延硅层上的源极 - 漏极扩散层，形成在源极和漏极之间的沟道区 区域，以及形成在沟道区上的栅电极，隔着栅绝缘膜的元件隔离区域夹在相邻的晶体管结构之间，其中形成在沟道区的下部的穿通阻挡层具有杂质浓度 高于沟道区域，并且源极 - 漏极扩散层不延伸以与用于元件隔离的绝缘膜的边缘部分重叠。

公开(公告)号：US06707706B2

公开(公告)日：2004-03-16

申请号：US10183156

申请日：2002-06-28

申请人： Akihiro Nitayama ,  Katsuhiko Hieda

发明人： Akihiro Nitayama ,  Katsuhiko Hieda

IPC分类号： G11C1124

CPC分类号： H01L27/10876 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L28/90

摘要： A semiconductor memory device comprises a plurality of columnar portions formed in memory cell array regions on a semiconductor substrate. The columnar portions are isolated from one another by a plurality of trenches, and these trenches have first and second bottoms that are different in depth. The semiconductor device comprises a plurality of cell transistors which include first diffusion layer regions formed in the first bottoms, which are shallower than the second bottoms, second diffusion layer regions formed in surface portions of the columnar portions, and a plurality of gate electrodes which are adjacent to both the first and second diffusion layer regions and extend along at least one side-surface portions of the columnar portions.

摘要翻译： 半导体存储器件包括形成在半导体衬底上的存储单元阵列区域中的多个柱状部分。 柱状部分通过多个沟槽彼此隔离，并且这些沟槽具有深度不同的第一和第二底部。 半导体器件包括多个单元晶体管，其包括形成在第一底部的第一扩散层区域，其比第二底部浅，形成在柱状部分的表面部分中的第二扩散层区域和多个栅电极 邻近第一和第二扩散层区域并且沿着柱状部分的至少一个侧表面部分延伸。

公开(公告)号：US06664592B2

公开(公告)日：2003-12-16

申请号：US10330280

申请日：2002-12-30

申请人： Seiji Inumiya ,  Tomohiro Saito ,  Atsushi Yagishita ,  Katsuhiko Hieda ,  Toshihiko Iinuma

发明人： Seiji Inumiya ,  Tomohiro Saito ,  Atsushi Yagishita ,  Katsuhiko Hieda ,  Toshihiko Iinuma

IPC分类号： H01L2976

CPC分类号： H01L29/495 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823437 ,  H01L29/41783 ,  H01L29/4941 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/78 ,  Y10S257/90

摘要： A semiconductor device includes a semiconductor substrate, a gate insulator film formed on a bottom surface and a side surface of a groove formed in the semiconductor substrate, a gate electrode having a lower portion buried in the groove on whose bottom and side surface the gate insulator film is formed, and an upper portion protruding a surface of said semiconductor substrate, and source region and a drain region formed on a surface of the semiconductor substrate in such a way as to sandwich the gate electrode. A thickness of the upper portion of the gate electrode protruding the surface of the semiconductor substrate is equal to or greater than twice a thickness of the lower portion of the gate electrode buried in the groove.

摘要翻译： 半导体器件包括半导体衬底，形成在半导体衬底的凹槽的底面和凹槽的侧面上的栅极绝缘体膜，栅电极，其下部埋设在沟槽中，栅极绝缘体的底部和侧表面上的栅极绝缘体 并且形成在半导体衬底的表面上的源极区域和漏极区域以夹着栅极电极的方式突出所述半导体衬底的表面的上部。 突出半导体衬底表面的栅电极的上部的厚度等于或大于埋在槽中的栅电极的下部的厚度的两倍。

公开(公告)号：US06611017B2

公开(公告)日：2003-08-26

申请号：US09816163

申请日：2001-03-26

申请人： Katsuhiko Hieda

发明人： Katsuhiko Hieda

IPC分类号： H01L27108

CPC分类号： H01L27/11502 ,  H01L27/10855 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/90 ,  H01L28/91

摘要： A plurality of storage node electrodes are formed on a semiconductor substrate. A capacitor insulating film is formed on the storage node electrodes. A plate electrode, facing the storage node electrodes, is formed on the capacitor insulating film. A cavity is formed in the plate electrode.

摘要翻译： 多个存储节点电极形成在半导体衬底上。 在存储节点电极上形成电容绝缘膜。 在电容器绝缘膜上形成面向存储节点电极的平板电极。 在平板电极中形成空腔。

公开(公告)号：US6072221A

公开(公告)日：2000-06-06

申请号：US105021

申请日：1998-06-26

申请人： Katsuhiko Hieda

发明人： Katsuhiko Hieda

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L29/417 ,  H01L29/78 ,  A01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/76897 ,  H01L29/41775 ,  H01L29/66545 ,  H01L29/6659

摘要： In the method of manufacturing a semiconductor device, according to the present invention, first, a dummy gate electrode consisting of a semiconductor layer and a non-metal cap layer formed on the semiconductor layer, is formed above a substrate. Then, diffusion layers are formed respectively on both sides of the dummy gate electrode. The dummy gate is used as a mask here, and thus the diffusion layers are self-aligned respectively with both sides of the dummy gate electrode. The formation of these diffusion layers requires a high-temperature heat treatment, however since the cap layer is made of a non-metal material, it is not melted down even in the high-temperature heat treatment. Next, the cap layer formed on the semiconductor layer is removed, and a gate groove made by the removal is filled with metal. Thus, a metal gate electrode made of a semiconductor layer and a metal layer is completed. As described above, in the present invention, first, a dummy gate electrode is formed of a non-metal cap layer, and the cap layer is removed after the formation of the diffusion layers, followed by filling the created gate groove with a metal. In this manner, the self-alignment of the diffusion layers and the metallization of the gate electrode can be achieved at the same time.

摘要翻译： 在本发明的半导体装置的制造方法中，首先，在基板的上方形成由在半导体层上形成的半导体层和非金属盖层构成的虚拟栅电极。 然后，分别在虚拟栅电极的两侧形成扩散层。 虚拟栅极用作掩模，因此扩散层分别与伪栅电极的两侧自对准。 这些扩散层的形成需要高温热处理，但是由于盖层由非金属材料制成，所以即使在高温热处理中也不会熔化。 接下来，去除形成在半导体层上的盖层，并且用金属填充通过去除制成的浇口槽。 因此，完成了由半导体层和金属层制成的金属栅电极。 如上所述，在本发明中，首先，由非金属盖层形成虚设栅电极，在形成扩散层之后除去盖层，然后用金属填充所形成的栅极槽。 以这种方式，可以同时实现扩散层的自对准和栅电极的金属化。

公开(公告)号：US6054355A

公开(公告)日：2000-04-25

申请号：US105956

申请日：1998-06-29

申请人： Seiji Inumiya ,  Tomohiro Saito ,  Atsushi Yagishita ,  Katsuhiko Hieda ,  Toshihiko Iinuma

发明人： Seiji Inumiya ,  Tomohiro Saito ,  Atsushi Yagishita ,  Katsuhiko Hieda ,  Toshihiko Iinuma

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/49

CPC分类号： H01L29/495 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823437 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/78 ,  H01L29/4941 ,  H01L29/66537 ,  Y10S257/90

摘要： A method of manufacturing a semiconductor device comprises the steps of forming a first film and a second film on a semiconductor substrate, selectively removing the second film, the first film and a top portion of the semiconductor substrate to form a first groove, burying a first insulator film in the first groove to form an isolation region, patterning the second film surrounded by the isolation region to form a dummy gate layer, doping the semiconductor substrate with an impurity using the dummy gate layer as a mask, forming a second insulator film on the semiconductor substrate surrounded by the dummy gate layer and the first insulator film, removing the dummy gate layer and the first film to form a second groove, forming a gate insulator film on the semiconductor substrate in the second groove, and forming a gate electrode on the gate insulator film in the second groove.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成第一膜和第二膜，选择性地去除第二膜，第一膜和半导体衬底的顶部以形成第一槽， 在第一沟槽中形成绝缘体膜以形成隔离区域，对由隔离区域包围的第二膜进行构图以形成伪栅极层，使用伪栅极层作为掩模将杂质掺杂到半导体衬底上，形成第二绝缘膜 所述半导体基板被所述伪栅极层和所述第一绝缘膜包围，去除所述伪栅极层和所述第一膜以形成第二沟槽，在所述第二沟槽中的所述半导体基板上形成栅极绝缘膜，并且形成栅电极 第二槽中的栅极绝缘膜。

公开(公告)号：US5747844A

公开(公告)日：1998-05-05

申请号：US736279

申请日：1996-10-24

申请人： Masami Aoki ,  Takashi Yamada ,  Hiroshi Takato ,  Tohru Ozaki ,  Katsuhiko Hieda ,  Akihiro Nitayama

发明人： Masami Aoki ,  Takashi Yamada ,  Hiroshi Takato ,  Tohru Ozaki ,  Katsuhiko Hieda ,  Akihiro Nitayama

IPC分类号： H01L21/822 ,  G11C11/401 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10817 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10882 ,  Y10S257/907

摘要： A plurality of bit line contacts provided on one bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL and a plurality of bit line contacts provided on an adjacent bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL which is different from the space in which a corresponding one of the bit line contacts formed on the former bit line is arranged.

公开(公告)号：US5508541A

公开(公告)日：1996-04-16

申请号：US124300

申请日：1993-09-20

申请人： Katsuhiko Hieda ,  Masami Aoki ,  Takeshi Hamamoto

发明人： Katsuhiko Hieda ,  Masami Aoki ,  Takeshi Hamamoto

IPC分类号： H01L27/108 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L27/108 ,  H01L27/10829

摘要： A MOS random access memory device includes a semiconductor substrate having a trench formed therein, and an array of memory cells on the substrate. Each of the memory cells includes a 1-bit data-storage capacitor and a transfer-gate MOS transistor. The capacitor includes an insulated layer buried in the trench, which serves as a storage node. An island-shaped semiconductor layer covers the storage-node layer at least partially on the substrate, and is coupled thereto. The transistor has a source and a drain defining a channel region therebetween in the substrate, and an insulated gate overlying the channel region. One of the source and drain is directly coupled to the island-shaped layer, while the other of them is contacted with a corresponding data-transfer line (bit line) associated therewith.

摘要翻译： MOS随机存取存储器件包括其中形成有沟槽的半导体衬底和衬底上的存储器单元的阵列。 每个存储单元包括1位数据存储电容器和转移栅极MOS晶体管。 电容器包括埋在沟槽中的绝缘层，其用作存储节点。 岛状半导体层至少部分地覆盖基板上的存储节点层，并且与其耦合。 晶体管具有源极和漏极，在衬底中限定其间的沟道区域，以及覆盖沟道区域的绝缘栅极。 源极和漏极中的一个直接耦合到岛状层，而另一个与与其相关联的相应数据传输线（位线）接触。

公开(公告)号：US5350708A

公开(公告)日：1994-09-27

申请号：US77744

申请日：1993-06-18

申请人： Atsushi Yagishita ,  Katsuhiko Hieda ,  Akihiro Nitayama ,  Fumio Horiguchi

发明人： Atsushi Yagishita ,  Katsuhiko Hieda ,  Akihiro Nitayama ,  Fumio Horiguchi

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70

CPC分类号： H01L27/10841 ,  H01L27/10823

摘要： A groove, which runs vertically and horizontally, is formed in a substrate, thereby a plurality of silicon pillars are formed in a matrix manner. A field oxidation film is formed on the central portion of the groove. A drain diffusion layer is formed on the upper portion of each silicon pillar, and a source diffusion layer is formed on the bottom portion of the groove. A gate electrode, serving as a word line, a storage node contacting the source diffusion layer, and a cell plate are sequentially buried to enclose the surroundings of each silicon pillar, and a bit line is formed in an uppermost layer, thereby a DRAM cell array is structured.

摘要翻译： 在衬底中形成垂直和水平延伸的槽，从而以矩阵形式形成多个硅柱。 在槽的中心部分形成场氧化膜。 在每个硅柱的上部形成漏极扩散层，在沟槽的底部形成有源极扩散层。 用作字线的栅电极，与源极扩散层接触的存储节点和单元板依次被埋置以包围每个硅柱的周围，并且在最上层形成位线，从而形成DRAM单元 阵列是结构化的

公开(公告)号：US08119196B2

公开(公告)日：2012-02-21

申请号：US12659071

申请日：2010-02-24

申请人： Osamu Arisumi ,  Masahiro Kiyotoshi ,  Katsuhiko Hieda

发明人： Osamu Arisumi ,  Masahiro Kiyotoshi ,  Katsuhiko Hieda

IPC分类号： B05D3/12

CPC分类号： B05B9/04 ,  B05B9/047 ,  B05C11/08 ,  B05C11/10

摘要： A semiconductor manufacturing apparatus comprises a discharge portion discharging a coating liquid onto a substrate; a gas supply tube supplying an inert gas into a liquid container that contains the coating liquid, and pressurizing an interior of the liquid container; a coating liquid supply tube airtightly supplying the coating liquid from the liquid container to the discharge portion using pressurization from the gas supply tube; a first connecting portion capable of attaching and detaching the liquid container to and from the coating liquid supply tube; a second connecting portion capable of attaching and detaching the liquid container to and from the gas supply tube; and a solvent supply tube supplying a solvent, which can dissolve the coating liquid, to the first connecting portion.

摘要翻译： 半导体制造装置包括将涂布液排出到基板上的排出部; 气体供给管，将惰性气体供给到容纳所述涂布液的液体容器内，对所述液体容器的内部进行加压; 涂料液体供给管通过来自气体供给管的加压将涂布液从液体容器密封地供给到排出部; 第一连接部分，其能够将液体容器附接到涂布液供应管和从涂布液供应管分离; 第二连接部分，其能够将液体容器附接到气体供应管和从气体供应管排出; 以及将能够溶解涂布液的溶剂供给到第一连接部的溶剂供给管。