Plasma processing, deposition and ALD methods
    41.
    发明授权
    Plasma processing, deposition and ALD methods 有权
    等离子体处理,沉积和ALD方法

    公开(公告)号:US08003000B2

    公开(公告)日:2011-08-23

    申请号:US12134554

    申请日:2008-06-06

    Applicant: Neal R. Rueger

    Inventor: Neal R. Rueger

    Abstract: A plasma processing method includes providing a substrate in a processing chamber, the substrate having a surface, and generating a plasma in the processing chamber. The plasma provides at least two regions that exhibit different plasma densities. The method includes exposing at least some of the surface to both of the at least two regions. Exposing the surface to both of the at least two regions may include rotating the plasma and may cyclically expose the surface to the plasma density differences. Exposing to both of the at least two regions may modify a composition and/or structure of the surface. The plasma may include a plasmoid characterized by a steady state plasma wave providing multiple plasma density lobes uniformly distributed about an axis of symmetry and providing plasma between the lobes exhibiting lower plasma densities. Depositing the layer can include ALD and exposure may remove an ALD precursor ligand.

    Abstract translation: 等离子体处理方法包括在处理室中提供衬底,所述衬底具有表面,并在处理室中产生等离子体。 等离子体提供至少两个显示不同等离子体密度的区域。 该方法包括将表面中的至少一些暴露于至少两个区域。 将表面暴露于至少两个区域中的两个可以包括旋转等离子体并且可以将表面循环地暴露于等离子体密度差。 暴露于至少两个区域的两者可以改变表面的组成和/或结构。 等离子体可以包括等离子体,其特征在于稳态等离子体波,其提供均匀分布在对称轴上的等离子体密度波瓣,并且在显示较低等离子体密度的波瓣之间提供等离子体。 沉积层可以包括ALD并且暴露可以去除ALD前体配体。

    INTEGRATED CIRCUIT INSPECTION SYSTEM
    42.
    发明申请
    INTEGRATED CIRCUIT INSPECTION SYSTEM 有权
    集成电路检测系统

    公开(公告)号:US20100141265A1

    公开(公告)日:2010-06-10

    申请号:US12705349

    申请日:2010-02-12

    CPC classification number: H01L22/12 B82Y15/00 H01J2237/2814 H01J2237/2818

    Abstract: Methods and systems that include a nanotube used as an emitter in the testing and fabrication of integrated circuits. The nanotube emits a signal to a substrate. Based on the signal or the electrical properties, e.g., current induced in the substrate by the signal, the region of the substrate is characterized. The characterization includes topology of the region of the substrate such as determining whether a recess in the substrate has a proper depth or other dimensions or characteristics of the substrate.

    Abstract translation: 包括在集成电路的测试和制造中用作发射极的纳米管的方法和系统。 纳米管向衬底发出信号。 基于信号或电特性,例如由信号在衬底中感应的电流,衬底的区域被表征。 表征包括衬底的区域的拓扑,例如确定衬底中的凹槽是否具有适当的深度或衬底的其他尺寸或特性。

    Integrated circuit inspection system
    43.
    发明授权
    Integrated circuit inspection system 失效
    集成电路检测系统

    公开(公告)号:US07662648B2

    公开(公告)日:2010-02-16

    申请号:US11216541

    申请日:2005-08-31

    CPC classification number: H01L22/12 B82Y15/00 H01J2237/2814 H01J2237/2818

    Abstract: Methods and systems that include a nanotube used as an emitter in the testing and fabrication of integrated circuits. The nanotube emits a signal to a substrate. Based on the signal or the electrical properties, e.g., current induced in the substrate by the signal, the region of the substrate is characterized. The characterization includes topology of the region of the substrate such as determining whether a recess in the substrate has a proper depth or other dimensions or characteristics of the substrate.

    Abstract translation: 包括在集成电路的测试和制造中用作发射极的纳米管的方法和系统。 纳米管向衬底发出信号。 基于信号或电特性,例如由信号在衬底中感应的电流,衬底的区域被表征。 表征包括衬底的区域的拓扑,例如确定衬底中的凹槽是否具有适当的深度或衬底的其他尺寸或特性。

    Protection in integrated circuits
    45.
    发明授权
    Protection in integrated circuits 失效
    集成电路保护

    公开(公告)号:US07494894B2

    公开(公告)日:2009-02-24

    申请号:US10231388

    申请日:2002-08-29

    CPC classification number: H01L21/76235

    Abstract: A method including, prior to a plasma heat-up operation, forming a liner on a structure coated with an insulator. And a method including forming a trench on a substrate, forming an insulator on the trench, and after forming a liner having a thickness of between about 50 angstroms and about 400 angstroms on the insulator, applying a plasma heat-up operation to the substrate.

    Abstract translation: 一种方法,包括在等离子体加热操作之前,在涂覆有绝缘体的结构上形成衬垫。 以及一种方法,包括在衬底上形成沟槽,在沟槽上形成绝缘体,并且在形成绝缘体上具有介于约50埃至约400埃之间的厚度的衬垫之后,对衬底施加等离子体加热操作。

    Transistor structures
    46.
    发明授权
    Transistor structures 有权
    晶体管结构

    公开(公告)号:US07459757B2

    公开(公告)日:2008-12-02

    申请号:US10050348

    申请日:2002-01-15

    Abstract: The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer. The nitrogen is subsequently thermally annealed within the layer to bond at least some of the nitrogen to silicon within the layer. The invention also encompasses a method of forming a transistor. A gate oxide layer is formed over a semiconductive substrate. The gate oxide layer comprises silicon dioxide. The gate oxide layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer, and the layer is maintained at less than or equal to 400° C. during the exposing. Subsequently, the nitrogen within the layer is thermally annealed to bond at least a majority of the nitrogen to silicon. At least one conductive layer is formed over the gate oxide layer. Source/drain regions are formed within the semiconductive substrate, and are gatedly connected to one another by the at least one conductive layer. The invention also encompasses transistor structures.

    Abstract translation: 本发明包括将氮掺入含氧化硅的层中的方法。 将含氧化硅的层暴露于含氮等离子体中以将氮引入层中。 氮气随后在层内热退火以将至少一些氮与硅结合在层内。 本发明还包括形成晶体管的方法。 在半导体衬底上形成栅氧化层。 栅氧化层包括二氧化硅。 将栅极氧化层暴露于含氮等离子体中以将氮引入层中,并且在暴露期间该层保持在小于或等于400℃。 随后,层内的氮被热退火以将至少大部分氮与硅结合。 在栅极氧化物层上形成至少一个导电层。 源极/漏极区域形成在半导体衬底内,并且通过至少一个导电层彼此门控连接。 本发明还包括晶体管结构。

    Plasma processing, deposition, and ALD methods
    47.
    发明授权
    Plasma processing, deposition, and ALD methods 失效
    等离子体处理,沉积和ALD方法

    公开(公告)号:US07402526B2

    公开(公告)日:2008-07-22

    申请号:US11492613

    申请日:2006-07-24

    Applicant: Neal R. Rueger

    Inventor: Neal R. Rueger

    Abstract: A plasma processing method includes providing a substrate in a processing chamber, the substrate having a surface, and generating a plasma in the processing chamber. The plasma provides at least two regions that exhibit different plasma densities. The method includes exposing at least some of the surface to both of the at least two regions. Exposing the surface to both of the at least two regions may include rotating the plasma and may cyclically expose the surface to the plasma density differences. Exposing to both of the at least two regions may modify a composition and/or structure of the surface. The plasma may include a plasmoid characterized by a steady state plasma wave providing multiple plasma density lobes uniformly distributed about an axis of symmetry and providing plasma between the lobes exhibiting lower plasma densities. Depositing the layer can include ALD and exposure may remove an ALD precursor ligand.

    Abstract translation: 等离子体处理方法包括在处理室中提供衬底,所述衬底具有表面,并在处理室中产生等离子体。 等离子体提供至少两个显示不同等离子体密度的区域。 该方法包括将表面中的至少一些暴露于至少两个区域。 将表面暴露于至少两个区域中的两个可以包括旋转等离子体并且可以将表面循环地暴露于等离子体密度差。 暴露于至少两个区域的两者可以改变表面的组成和/或结构。 等离子体可以包括等离子体,其特征在于稳态等离子体波,其提供均匀分布在对称轴上的等离子体密度波瓣,并且在显示较低等离子体密度的波瓣之间提供等离子体。 沉积层可以包括ALD并且暴露可以去除ALD前体配体。

    Plasma processing, deposition and ALD methods
    48.
    发明授权
    Plasma processing, deposition and ALD methods 有权
    等离子体处理,沉积和ALD方法

    公开(公告)号:US07323400B2

    公开(公告)日:2008-01-29

    申请号:US10930895

    申请日:2004-08-30

    Applicant: Neal R. Rueger

    Inventor: Neal R. Rueger

    Abstract: A plasma processing method includes providing a substrate in a processing chamber, the substrate having a surface, and generating a plasma in the processing chamber. The plasma provides at least two regions that exhibit different plasma densities. The method includes exposing at least some of the surface to both of the at least two regions. Exposing the surface to both of the at least two regions may include rotating the plasma and may cyclically expose the surface to the plasma density differences. Exposing to both of the at least two regions may modify a composition and/or structure of the surface. The plasma may include a plasmoid characterized by a steady state plasma wave providing multiple plasma density lobes uniformly distributed about an axis of symmetry and providing plasma between the lobes exhibiting lower plasma densities. Depositing the layer can include ALD and exposure may remove an ALD precursor ligand.

    Abstract translation: 等离子体处理方法包括在处理室中提供衬底,所述衬底具有表面,并在处理室中产生等离子体。 等离子体提供至少两个显示不同等离子体密度的区域。 该方法包括将表面中的至少一些暴露于至少两个区域。 将表面暴露于至少两个区域中的两个可以包括旋转等离子体并且可以将表面循环地暴露于等离子体密度差。 暴露于至少两个区域的两者可以改变表面的组成和/或结构。 等离子体可以包括等离子体,其特征在于稳态等离子体波,其提供均匀分布在对称轴上的等离子体密度波瓣,并且在显示较低等离子体密度的波瓣之间提供等离子体。 沉积层可以包括ALD并且暴露可以去除ALD前体配体。

    Methods of forming semiconductor constructions
    49.
    发明授权
    Methods of forming semiconductor constructions 失效
    形成半导体结构的方法

    公开(公告)号:US07276426B2

    公开(公告)日:2007-10-02

    申请号:US11137752

    申请日:2005-05-25

    Applicant: Neal R. Rueger

    Inventor: Neal R. Rueger

    CPC classification number: H01L21/76229

    Abstract: The invention includes a method of forming a semiconductor construction. A semiconductor substrate is placed within a reaction chamber. The substrate comprises a center region and an edge region surrounding the center region. The substrate comprises openings within the center region, and openings within the edge region. While the substrate is within the reaction chamber, a layer of insulative material is formed across the substrate. The layer is thicker over the one of the center region and edge region than over the other of the center region and edge region. The layer is exposed to an etch which removes the insulative material faster from over the one of the center region and edge region than from over the other of the center region and edge region.

    Abstract translation: 本发明包括形成半导体结构的方法。 将半导体衬底放置在反应室内。 衬底包括中心区域和围绕中心区域的边缘区域。 基板包括中心区域内的开口,以及边缘区域内的开口。 当衬底在反应室内时,跨越衬底形成一层绝缘材料。 该层在中心区域和边缘区域中的一个上比在中心区域和边缘区域中的另一个厚。 该层暴露于从中心区域和边缘区域中的一个上移除绝缘材料的蚀刻,而不是从中心区域和边缘区域的另一个移除绝缘材料。

    Methods of filling gaps using high density plasma chemical vapor deposition
    50.
    发明授权
    Methods of filling gaps using high density plasma chemical vapor deposition 有权
    使用高密度等离子体化学气相沉积填充间隙的方法

    公开(公告)号:US07273793B2

    公开(公告)日:2007-09-25

    申请号:US11115854

    申请日:2005-04-25

    Abstract: The invention includes a method of filling gaps in a semiconductor substrate. A substrate and a gas mixture containing at least one heavy-hydrogen compound are provided within a reaction chamber. The gas mixture is reacted to form a layer of material over the substrate by simultaneous deposition and etch of the layer. The layer of material fills the gap such that the material within the gap is essentially void-free. The invention includes a method of providing improved deposition rate uniformity. A material is deposited over a surface in the presence of at least one gas selected from the group consisting of D2, HD, DT, T2 and TH. The net deposition rate during the deposition has a degree of variance across the surface which is measurably improved relative to a corresponding degree of variance that occurs during deposition utilizing H2 under otherwise substantially identical conditions.

    Abstract translation: 本发明包括填充半导体衬底中的间隙的方法。 在反应室内设置底物和含有至少一种重氢化合物的气体混合物。 通过同时沉积和蚀刻该层,使气体混合物反应以在衬底上形成一层材料。 材料层填充间隙,使得间隙内的材料基本上无空隙。 本发明包括提供改进的沉积速率均匀性的方法。 在选自由D 2,HD,DT,T 2和TH组成的组中的至少一种气体存在下,材料沉积在表面上。 沉积期间的净沉积速率在整个表面上具有相对于在其它实质上相同的条件下利用H 2 N沉积期间发生的相应的变化程度可以显着改善的表面上的变化程度。

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