公开(公告)号：US06730570B2

公开(公告)日：2004-05-04

申请号：US10348017

申请日：2003-01-22

申请人： Seung-Mok Shin ,  Jae-Jong Han ,  Ki-Hyun Hwang

发明人： Seung-Mok Shin ,  Jae-Jong Han ,  Ki-Hyun Hwang

IPC分类号： H01L21336

CPC分类号： H01L21/76897 ,  H01L21/76831 ,  H01L29/6656

摘要： A method for forming a self-aligned contact in a semiconductor device which can reduce process failures and a method for manufacturing a semiconductor device that includes the self-aligned contact are provided. A self-aligned contact hole is formed in an interlayer dielectric film to expose a portion of the substrate between conductive structures formed thereon. A buffer layer is formed on a sidewall of the self-aligned contact hole, on the bottom of the self-aligned contact hole, and on the interlayer dielectric film such that the thickness of the buffer layer at an upper portion of the self-aligned contact hole is greater than the thickness of the buffer layer at the bottom of the self-aligned contact hole. After removing the portion of the buffer layer on the bottom of the self-aligned contact hole, a contact is formed in the self-aligned contact hole to make contact with the substrate.

摘要翻译： 提供了一种用于在可以减少工艺故障的半导体器件中形成自对准接触的方法以及包括自对准接触的半导体器件的制造方法。 在层间电介质膜中形成自对准接触孔，以在其上形成的导电结构之间露出基板的一部分。 在自对准接触孔的侧壁，自对准接触孔的底部和层间电介质膜上形成缓冲层，使得缓冲层在自对准的上部的厚度 接触孔大于自对准接触孔底部缓冲层的厚度。 在自对准接触孔的底部上移除缓冲层的部分之后，在自对准接触孔中形成接触以与衬底接触。

公开(公告)号：US06700153B2

公开(公告)日：2004-03-02

申请号：US10136385

申请日：2002-05-02

申请人： Jung-Hwan Oh ,  Ki-Hyun Hwang ,  Jae-Young Park ,  In-Seak Hwang ,  Young-Wook Park

发明人： Jung-Hwan Oh ,  Ki-Hyun Hwang ,  Jae-Young Park ,  In-Seak Hwang ,  Young-Wook Park

IPC分类号： H01L27108

CPC分类号： H01L28/91 ,  H01L27/10855 ,  Y10T29/5111

摘要： An etch stop layer is formed over a surface of an interlayer insulating layer and over a surface of a conductive plug extending at a depth from the surface of the interlayer insulating layer. A lower mold layer is deposited over the etch stop layer, and a wet etch rate of the lower mold layer is adjusted by adding dopants to the lower mold layer during formation of the lower mold layer, and by annealing the lower mold layer. An upper mold layer is then deposited over the surface of the lower mold layer, such that a wet etch rate of the upper mold layer is less than the adjusted wet etch rate of the lower mold layer. The upper mold layer, the lower mold layer and the etch stop layer are then subjected to dry etching to form an opening therein which exposes at least a portion of the surface of the contact plug. Then a wet etching of the upper mold layer and the lower mold layer is performed so as to increase a size of the opening at the lower mold layer and so at to expose a surface portion of the etch stop layer adjacent the surface of the conductive plug. A conductive material is then deposited over the surface of the opening in the upper and lower mold layers to define a capacitor electrode.

公开(公告)号：US09111897B2

公开(公告)日：2015-08-18

申请号：US13716859

申请日：2012-12-17

申请人： Jung-Geun Jee ,  Jin-Gyun Kim ,  Ji-Hoon Choi ,  Ki-Hyun Hwang

发明人： Jung-Geun Jee ,  Jin-Gyun Kim ,  Ji-Hoon Choi ,  Ki-Hyun Hwang

IPC分类号： H01L21/336 ,  H01L21/36 ,  H01L29/66 ,  H01L21/02 ,  H01L27/108 ,  H01L27/115 ,  H01L21/285 ,  H01L21/768 ,  C23C16/24

CPC分类号： H01L21/36 ,  C23C16/24 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02494 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28525 ,  H01L21/28556 ,  H01L21/76876 ,  H01L21/76877 ,  H01L27/10888 ,  H01L27/11582 ,  H01L29/66666

摘要： A method of forming a polysilicon layer includes providing a silicon precursor onto an object loaded in a process chamber to form a seed layer. The silicon precursor includes a nitrogen containing silicon precursor and a chlorine containing silicon precursor. The method further includes providing a silicon source on the seed layer.

摘要翻译： 形成多晶硅层的方法包括将硅前体提供到加载在处理室中的物体上以形成种子层。 硅前体包括含氮的硅前体和含氯的硅前体。 该方法还包括在种子层上提供硅源。

公开(公告)号：US08614476B2

公开(公告)日：2013-12-24

申请号：US13564992

申请日：2012-08-02

申请人： Hong-Suk Kim ,  Yong-Seok Kim ,  Hun-Hyeong Lim ,  Ki-Hyun Hwang

发明人： Hong-Suk Kim ,  Yong-Seok Kim ,  Hun-Hyeong Lim ,  Ki-Hyun Hwang

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881

摘要： Non-volatile memory devices, and fabricating methods thereof, include a floating gate over a substrate, a lower barrier layer including a first lower barrier layer on the upper surface of the floating gate, and a second lower barrier layer on a side surface of the floating gate to have a thickness smaller than a thickness of the first lower barrier layer, an inter-gate dielectric layer over the lower barrier layer, and a control gate over the inter-gate dielectric layer.

摘要翻译： 非易失性存储器件及其制造方法包括在衬底上的浮置栅极，在浮置栅极的上表面上包括第一下阻挡层的下势垒层和位于浮置栅极的侧表面上的第二下势垒层 浮栅的厚度小于第一下阻挡层的厚度，下阻挡层上的栅极间电介质层和栅极间电介质层上的控制栅极。

公开(公告)号：US08294198B2

公开(公告)日：2012-10-23

申请号：US12704312

申请日：2010-02-11

申请人： Dong-Chul Yoo ,  Eun-Ha Lee ,  Byong-Ju Kim ,  Hyung-Ik Lee ,  Sung Heo ,  Han-Mei Choi ,  Chan-Hee Park ,  Ki-Hyun Hwang

发明人： Dong-Chul Yoo ,  Eun-Ha Lee ,  Byong-Ju Kim ,  Hyung-Ik Lee ,  Sung Heo ,  Han-Mei Choi ,  Chan-Hee Park ,  Ki-Hyun Hwang

IPC分类号： H01L29/72

CPC分类号： H01L29/792 ,  H01L21/7605 ,  H01L21/7607 ,  H01L21/76224 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/4234

摘要： A semiconductor integrated circuit device is provided. The semiconductor integrated circuit device includes a plurality of isolation regions which are formed within a semiconductor substrate and define active regions. A tunnel layer and a trap seed layer are formed in each of the active regions and are sequentially stacked between the isolation regions. A trap layer is formed on the trap seed layer and protrudes further than a top surface of each of the isolation regions. A blocking layer is formed on the trap layer. A gate electrode is formed on the blocking layer.

摘要翻译： 提供了一种半导体集成电路器件。 半导体集成电路器件包括形成在半导体衬底内并限定有源区的多个隔离区。 在每个有源区域中形成隧道层和陷阱种子层，并且依次堆叠在隔离区域之间。 陷阱层形成在捕获种子层上并且比每个隔离区的顶表面更突出。 在捕获层上形成阻挡层。 在阻挡层上形成栅电极。

公开(公告)号：US20120187470A1

公开(公告)日：2012-07-26

申请号：US13340968

申请日：2011-12-30

申请人： Jung-Hwan KIM ,  Sung-Ho Heo ,  Jae-Ho Choi ,  Hun-Hyeong Lim ,  Ki-Hyun Hwang ,  Woo-Sung Lee

发明人： Jung-Hwan KIM ,  Sung-Ho Heo ,  Jae-Ho Choi ,  Hun-Hyeong Lim ,  Ki-Hyun Hwang ,  Woo-Sung Lee

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/11531

摘要： A method of forming a gate structure includes forming a tunnel insulation layer pattern on a substrate, forming a floating gate on the tunnel insulation layer pattern, forming a dielectric layer pattern on the floating gate, the dielectric layer pattern including a first oxide layer pattern, a nitride layer pattern on the first oxide layer pattern, and a second oxide layer pattern on the nitride layer pattern, the second oxide layer pattern being formed by performing an anisotropic plasma oxidation process on the nitride layer, such that a first portion of the second oxide layer pattern on a top surface of the floating gate has a larger thickness than a second portion of the second oxide layer pattern on a sidewall of the floating gate, and forming a control gate on the second oxide layer.

摘要翻译： 形成栅极结构的方法包括在衬底上形成隧道绝缘层图案，在隧道绝缘层图案上形成浮栅，在浮栅上形成电介质层图案，电介质层图案包括第一氧化层图案， 所述第一氧化物层图案上的氮化物层图案和所述氮化物层图案上的第二氧化物层图案，所述第二氧化物层图案通过在所述氮化物层上进行各向异性等离子体氧化处理而形成，使得所述第二氧化物层图案的第二部分 在浮置栅极的顶表面上的氧化物层图案具有比浮置栅极的侧壁上的第二氧化物层图案的第二部分更大的厚度，并且在第二氧化物层上形成控制栅极。

公开(公告)号：US20120115293A1

公开(公告)日：2012-05-10

申请号：US13287509

申请日：2011-11-02

申请人： Jin-Tae NOH ,  Hun-Hyeong Lim ,  Ki-Hyun Hwang ,  Jin-Gyun Kim ,  Sang-Ryol Yang

发明人： Jin-Tae NOH ,  Hun-Hyeong Lim ,  Ki-Hyun Hwang ,  Jin-Gyun Kim ,  Sang-Ryol Yang

IPC分类号： H01L21/336 ,  H01L21/8234 ,  B82Y40/00

CPC分类号： H01L27/1157 ,  H01L27/10855 ,  H01L27/11582

摘要： In a method of manufacturing a semiconductor device, a plurality of sacrificial layers and a plurality of insulating interlayers are repeatedly and alternately on a substrate. The insulating interlayers include a different material from a material of the sacrificial layers. At least one opening through the insulating interlayers and the sacrificial layers are formed. The at least one opening exposes the substrate. The seed layer is formed on an inner wall of the at least one opening using a first silicon source gas. A polysilicon channel is formed in the at least one opening by growing the seed layer. The sacrificial layers are removed to form a plurality of grooves between the insulating interlayers. A plurality of gate structures is formed in the grooves, respectively.

摘要翻译： 在制造半导体器件的方法中，多个牺牲层和多个绝缘中间层在衬底上重复交替。 绝缘夹层包括与牺牲层的材料不同的材料。 通过绝缘夹层和牺牲层形成至少一个开口。 至少一个开口露出基板。 种子层使用第一硅源气体形成在至少一个开口的内壁上。 通过种植种子层在至少一个开口中形成多晶硅沟道。 去除牺牲层以在绝缘夹层之间形成多个凹槽。 在槽中分别形成有多个栅极结构。

公开(公告)号：US20120098139A1

公开(公告)日：2012-04-26

申请号：US13246152

申请日：2011-09-27

申请人： Soo-Doo Chae ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Dong-Chul Yoo

发明人： Soo-Doo Chae ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Dong-Chul Yoo

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L27/11582 ,  H01L29/7926

摘要： A vertical memory device includes a channel, a ground selection line (GSL), word lines, a string selection line (SSL), and a contact. The channel includes a vertical portion and a horizontal portion. The vertical portion extends in a first direction substantially perpendicular to a top surface of a substrate, and the horizontal portion is connected to the vertical portion and parallel to the top surface of the substrate. The GSL, the word lines and the SSL are formed on a sidewall of the vertical portion of the channel sequentially in the first direction, and are spaced apart from each other. The contact is on the substrate and electrically connected to the horizontal portion of the channel.

摘要翻译： 垂直存储器件包括通道，接地选择线（GSL），字线，字符串选择线（SSL）和触点。 通道包括垂直部分和水平部分。 垂直部分在基本上垂直于基板的顶表面的第一方向上延伸，并且水平部分连接到垂直部分并且平行于基板的顶表面。 GSL，字线和SSL沿着第一方向依次形成在通道的垂直部分的侧壁上，并且彼此间隔开。 触点位于基板上并电连接到通道的水平部分。

公开(公告)号：US08008154B2

公开(公告)日：2011-08-30

申请号：US12188482

申请日：2008-08-08

申请人： Young-Jin Noh ,  Bon-Young Koo ,  Si-Young Choi ,  Ki-Hyun Hwang ,  Chul-Sung Kim ,  Sung-Kweon Baek ,  Jin-Hwa Heo

发明人： Young-Jin Noh ,  Bon-Young Koo ,  Si-Young Choi ,  Ki-Hyun Hwang ,  Chul-Sung Kim ,  Sung-Kweon Baek ,  Jin-Hwa Heo

IPC分类号： H01L21/336

CPC分类号： H01L29/42324 ,  H01L21/0214 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/28273 ,  H01L21/3145 ,  H01L21/31662

摘要： Methods of forming an insulating film include forming an insulating film on a substrate. A first impurity is injected into the insulating film using a thermal process under a first set of processing conditions to form a first impurity concentration peak in a lower portion of the insulating film. A second impurity is injected into the insulating film using the thermal process under a second set of processing conditions, different from the first set of processing conditions, to form a second impurity concentration peak in an upper portion of the insulating film. Injecting the first impurity and injecting the second impurity may be carried out without using plasma and the first impurity concentration peak may be higher than the second impurity concentration peak.

摘要翻译： 形成绝缘膜的方法包括在基板上形成绝缘膜。 使用第一组处理条件下的热处理将第一杂质注入绝缘膜，以在绝缘膜的下部形成第一杂质浓度峰。 在与第一组处理条件不同的第二组处理条件下，使用热处理将第二杂质注入到绝缘膜中，以在绝缘膜的上部形成第二杂质浓度峰。 注入第一杂质并注入第二杂质可以在不使用等离子体的情况下进行，并且第一杂质浓度峰可以高于第二杂质浓度峰。

公开(公告)号：US07622383B2

公开(公告)日：2009-11-24

申请号：US11421111

申请日：2006-05-31

申请人： Jin-Gyun Kim ,  Ki-Hyun Hwang ,  Jin-Tae Noh ,  Hong-Suk Kim ,  Sung-Hae Lee

发明人： Jin-Gyun Kim ,  Ki-Hyun Hwang ,  Jin-Tae Noh ,  Hong-Suk Kim ,  Sung-Hae Lee

IPC分类号： H01L21/44

CPC分类号： H01L27/11521 ,  C23C16/24 ,  C23C16/45527 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/28273 ,  H01L21/28525 ,  H01L27/115 ,  H01L29/66825

摘要： A method of forming a conductive polysilicon thin film and a method of manufacturing a semiconductor device using the same are provided. The method of forming a conductive polysilicon thin film may comprise simultaneously supplying a Si precursor having halogen elements as a first reactant and a dopant to a substrate to form a first reactant adsorption layer that is doped with impurities on the substrate and then supplying a second reactant having H (hydrogen) to the first reactant adsorption layer to react the H of the second reactant with the halogen elements of the first reactant to form a doped Si atomic layer on the substrate.

摘要翻译： 提供一种形成导电多晶硅薄膜的方法和使用其制造半导体器件的方法。 形成导电多晶硅薄膜的方法可以包括同时向衬底提供具有卤素元素的Si前体作为第一反应物和掺杂剂以形成在衬底上掺杂杂质的第一反应物吸附层，然后提供第二反应物 对第一反应物吸附层具有H（氢）以使第二反应物的H与第一反应物的卤素元素反应，以在衬底上形成掺杂的Si原子层。