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    Variable thickness gate oxide transcap
    41.
    发明授权
    Variable thickness gate oxide transcap 有权

    公开(公告)号：US10580908B2

    公开(公告)日：2020-03-03

    申请号：US15947667

    申请日：2018-04-06

    Applicant: QUALCOMM Incorporated

    Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

    IPC: H01L29/93 ,  H01L27/08 ,  H01L29/06 ,  H01G7/06 ,  H01L29/739 ,  H01L29/94

    Abstract: Aspects of the present disclosure provide semiconductor variable capacitor devices. In one embodiment, a semiconductor variable capacitor includes a gate oxide layer comprising a first layer portion with a first thickness and a second layer portion with a second thickness; a first non-insulative region disposed above the gate oxide layer; a first semiconductor region disposed beneath the gate oxide layer; a second semiconductor region disposed beneath the gate oxide layer and adjacent to the first semiconductor region, wherein the second semiconductor region comprises a different doping type than the first semiconductor region a second non-insulative region coupled to the first semiconductor region; and a control terminal coupled to a control region coupled to the second semiconductor region such that a first capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region.

    SRAM read preferred bit cell with write assist circuit
    46.
    发明授权
    SRAM read preferred bit cell with write assist circuit 有权
    SRAM通过写辅助电路读取优先位单元

    公开(公告)号：US09583178B2

    公开(公告)日：2017-02-28

    申请号：US13741869

    申请日：2013-01-15

    Applicant: QUALCOMM Incorporated

    Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Bin Yang ,  Choh Fei Yeap

    IPC: G11C11/00 ,  G11C11/412 ,  G11C11/419

    CPC classification number: G11C11/412 ,  G11C11/419

    Abstract: Methods and apparatuses for static memory cells. A static memory cell may include a first pass gate transistor including a first back gate node and a second pass gate transistor including a second back gate node. The static memory cell may include a first pull down transistor including a third back gate node and a second pull down transistor including a fourth back gate node. The source node of the first pull down transistor, source node of the second pull down transistor, and first, second, third, and fourth back gate nodes are electrically coupled to each other to form a common node.

    Abstract translation: 静态存储单元的方法和装置。 静态存储单元可以包括第一栅极晶体管，其包括第一背栅极节点和包括第二后栅极节点的第二栅极晶体管。 静态存储单元可以包括包括第三后栅极节点的第一下拉晶体管和包括第四背栅极节点的第二下拉晶体管。 第一下拉晶体管的源节点，第二下拉晶体管的源节点以及第一，第二，第三和第四后门节点彼此电耦合以形成公共节点。

    Vertical tunnel field effect transistor
    49.
    发明授权
    Vertical tunnel field effect transistor 有权
    垂直隧道场效应晶体管

    公开(公告)号：US09425296B2

    公开(公告)日：2016-08-23

    申请号：US14021795

    申请日：2013-09-09

    Applicant: QUALCOMM Incorporated

    Inventor： Xia Li ,  Ming Cai ,  Bin Yang

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/739

    CPC classification number: H01L29/66977 ,  H01L29/66356 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/7827

    Abstract: A tunnel field transistor (TFET) device includes a fin structure that protrudes from a substrate surface. The fin structure includes a base portion proximate to the substrate surface, a top portion, and a first pair of sidewalls extending from the base portion to the top portion. The first pair of sidewalls has a length corresponding to a length of the fin structure. The fin structure also includes a first doped region having a first dopant concentration at the base portion of the fin structure. The fin structure also includes a second doped region having a second dopant concentration at the top portion of the fin structure. The TFET device further includes a gate including a first conductive structure neighboring a first sidewall of the first pair of sidewalls. A dielectric layer electrically isolates the first conductive structure from the first sidewall.

    Abstract translation: 隧道场晶体管（TFET）器件包括从衬底表面突出的鳍结构。 翅片结构包括靠近基底表面的基部，顶部和从基部延伸到顶部的第一对侧壁。 第一对侧壁的长度对应于翅片结构的长度。 翅片结构还包括在鳍结构的基部处具有第一掺杂剂浓度的第一掺杂区域。 鳍结构还包括在鳍结构的顶部具有第二掺杂剂浓度的第二掺杂区。 TFET器件还包括栅极，其包括与第一对侧壁的第一侧壁相邻的第一导电结构。 电介质层将第一导电结构与第一侧壁电隔离。

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