公开(公告)号：US20240345745A1

公开(公告)日：2024-10-17

申请号：US18643662

申请日：2024-04-23

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Brent Steven Haukness

IPC: G06F3/06

CPC classification number: G06F3/0629 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory module includes one or more memory devices and a memory interface chip coupled to the one or more memory devices via one or more communication links. The memory module further includes a persistent memory storing one or more sets of training and calibration settings corresponding to communication over the one or more communication links, where the one or more sets of training and calibration settings are stored in the persistent memory before operation of the memory module and used to configure one or more components of the memory interface chip during the operation of the memory module.

公开(公告)号：US20240146336A1

公开(公告)日：2024-05-02

申请号：US18498832

申请日：2023-10-31

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Michael Alexander Hamburg ,  John Eric Linstadt ,  Evan Lawrence Erickson

IPC: H03M13/00 ,  H03M13/15 ,  H03M13/43

CPC classification number: H03M13/6312 ,  H03M13/159 ,  H03M13/43

Abstract: Aspects and implementations include systems and techniques that detect and correct failure of data storage and communication operations, including obtaining a first plurality of values, selecting a first plurality of error correction values to generate a first codeword, wherein the first codeword is associated with a plurality of syndrome values that encode a second subset of the first plurality of values, and causing a first processing device or a second processing device to restore the first plurality of values based on the first codeword.

公开(公告)号：US11972121B2

公开(公告)日：2024-04-30

申请号：US17800601

申请日：2021-02-25

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Liji Gopalakrishnan

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0629 ,  G06F3/0673

Abstract: Power consumption in a three-dimensional stack of integrated-circuit memory dies is reduced through selective enabling/disabling of physical signaling interfaces in those dies in response to early transmission of chip identifier information relative to command execution.

公开(公告)号：US11804250B2

公开(公告)日：2023-10-31

申请号：US17665760

申请日：2022-02-07

Applicant: Rambus Inc.

Inventor： James E. Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/08 ,  G11C5/02 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10

CPC classification number: G11C7/1039 ,  G11C5/025 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/222 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

公开(公告)号：US20220334738A1

公开(公告)日：2022-10-20

申请号：US17721176

申请日：2022-04-14

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Brent Steven Haukness

IPC: G06F3/06

Abstract: A memory module includes one or more memory devices and a memory interface chip coupled to the one or more memory devices via one or more communication links. The memory module further includes a persistent memory storing one or more sets of training and calibration settings corresponding to communication over the one or more communication links, where the one or more sets of training and calibration settings are stored in the persistent memory before operation of the memory module and used to configure one or more components of the memory interface chip during the operation of the memory module.

公开(公告)号：US20220165326A1

公开(公告)日：2022-05-26

申请号：US17439215

申请日：2020-03-16

Applicant: RAMBUS INC.

Inventor： Frederick Ware ,  Thomas Vogelsang ,  Michael Raymond Miller ,  Collins Williams

IPC: G11C11/4093 ,  G11C11/408 ,  G11C11/4076 ,  G11C8/18 ,  G06F12/0895

Abstract: Disclosed is a memory system that has a memory controller and may have a memory component. The memory component may be a dynamic random access memory (DRAM). The memory controller is connectable to the memory component. The memory component has at least one data row and at least one tag row different from and associated with the at least one data row. The memory system is to implement a cache having multiple ways to hold a data group. The memory controller is operable in each of a plurality of operating modes. The operating modes include a first operating mode and a second operating mode. The first operating mode and the second operating mode have differing addressing and timing for accessing the data group. The memory controller has cache read logic that sends a cache read command, cache results logic that receives a response from the memory component, and cache fetch logic.

公开(公告)号：US20210200680A1

公开(公告)日：2021-07-01

申请号：US17058492

申请日：2019-05-31

Applicant: RAMBUS INC.

Inventor： Thomas Vogelsang ,  Frederick A. Ware ,  Michael Raymond Miller ,  Collins Williams

IPC: G06F12/0864

Abstract: Disclosed is a dynamic random access memory that has columns, data rows, tag rows and comparators. Each comparator compares address bits and tag information bits from the tag rows to determine a cache hit and generate address bits to access data information in the DRAM as a multiway set associative cache.

公开(公告)号：US11029216B1

公开(公告)日：2021-06-08

申请号：US16528496

申请日：2019-07-31

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Frederick A. Ware

IPC: H03K19/0175 ,  G05F1/56 ,  G01K7/01 ,  G05F3/24

Abstract: During operation of an IC component within a first range of temperatures, a first bias voltage is applied to a first substrate region disposed adjacent a first plurality of transistors to effect a first threshold voltage for the first plurality of transistors. During operation of the IC component within a second range of temperatures that is distinct from and lower than the first range of temperatures, a second bias voltage is applied to the first substrate region to effect a second threshold voltage for the first plurality of transistors that is at least as low as the first threshold voltage.

公开(公告)号：US11012649B2

公开(公告)日：2021-05-18

申请号：US16503383

申请日：2019-07-03

Applicant: Rambus Inc.

Inventor： Michael Guidash ,  Jay Endsley ,  John Ladd ,  Thomas Vogelsang ,  Craig M. Smith

IPC: H04N5/374 ,  H04N5/357 ,  H04N5/365 ,  H04N5/376 ,  H04N5/378 ,  H04N5/355 ,  H01L27/146

Abstract: A control pulse is generated a first control signal line coupled to a transfer gate of a pixel to enable photocharge accumulated within a photosensitive element of the pixel to be transferred to a floating diffusion node, the first control signal line having a capacitive coupling to the floating diffusion node. A feedthrough compensation pulse is generated on a second signal line of the pixel array that also has a capacitive coupling to the floating diffusion node. The feedthrough compensation pulse is generated with a pulse polarity opposite the pulse polarity of the control pulse and is timed to coincide with the control pulse such that capacitive feedthrough of the control pulse to the floating diffusion node is reduced.

公开(公告)号：US11004530B2

公开(公告)日：2021-05-11

申请号：US16378304

申请日：2019-04-08

Applicant: RAMBUS INC.

Inventor： Thomas Vogelsang ,  William Ng ,  Frederick A. Ware

IPC: G11C29/02 ,  G11C5/06 ,  G01R31/28 ,  G11C5/02 ,  G11C29/04 ,  H01L25/065 ,  G11C8/10 ,  H01L21/66

Abstract: Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TSV to at least one of a test input and a test evaluation circuit.