公开(公告)号：US20060051933A1

公开(公告)日：2006-03-09

申请号：US11198038

申请日：2005-08-05

申请人： Sameer Pendharkar

发明人： Sameer Pendharkar

IPC分类号： H01L21/76

CPC分类号： H01L29/0653 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0692 ,  H01L29/42368 ,  H01L29/7835

摘要： A drain-extended metal-oxide-semiconductor transistor (40) with improved robustness in breakdown characteristics is disclosed. Field oxide isolation structures (29c) are disposed between the source region (30) and drain contact regions (32a, 32b, 32c) to break the channel region of the transistor into parallel sections. The gate electrode (35) extends over the multiple channel regions, and the underlying well (26) and thus the drift region (DFT) of the transistor extends along the full channel width. Channel stop doped regions (33) underlie the field oxide isolation structures (29c), and provide conductive paths for carriers during breakdown. Parasitic bipolar conduction, and damage due to that conduction, is therefore avoided.

摘要翻译： 公开了具有改进的击穿特性鲁棒性的漏极延伸金属氧化物半导体晶体管（40）。 场源氧化物隔离结构（29c）设置在源极区域（30）和漏极接触区域（32a，32b，32c）之间，以将晶体管的沟道区域断开成平行段。 栅极电极（35）在多个沟道区域上延伸，并且下面的阱（26）以及晶体管的漂移区域（DFT）沿整个沟道宽度延伸。 通道阻挡掺杂区域（33）位于场氧化物隔离结构（29c）的下面，并且在击穿期间为载体提供导电路径。 因此避免了寄生双极导电和由于导电导致的损坏。

公开(公告)号：US20060022278A1

公开(公告)日：2006-02-02

申请号：US11187472

申请日：2005-07-22

申请人： Shanjen Pan ,  James Todd ,  Sameer Pendharkar

发明人： Shanjen Pan ,  James Todd ,  Sameer Pendharkar

IPC分类号： H01L21/8238 ,  H01L29/94

CPC分类号： H01L29/7833 ,  H01L21/823418 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/0922

摘要： A CMOS integrated circuit (15A-B-C) includes both relatively low-power (124, 126) and high-power (132, 134) CMOS transistors on the same chip. A 20V, relatively high-power PMOS device (134) includes a heavily doped N-well drain region (70). A 20V, relatively high-power NMOS device (132) includes heavily doped P-type buried layers (76, 78) underneath the source (94) and drain regions (96) and spanning the gap between the P-well gate (90F) and adjacent P-well isolation regions (46, 50).

公开(公告)号：US20050253217A1

公开(公告)日：2005-11-17

申请号：US10832009

申请日：2004-04-26

申请人： Shanjen Pan ,  Sameer Pendharkar ,  James Todd

发明人： Shanjen Pan ,  Sameer Pendharkar ,  James Todd

IPC分类号： H01L21/8234 ,  H01L21/266 ,  H01L21/336 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/423 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L21/266 ,  H01L27/0623 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835 ,  H01L2029/42388

摘要： The present invention provides, in one embodiment, a transistor (100). The transistor (100) comprises a doped semiconductor substrate (105) and a gate structure (110) over the semiconductor substrate (105), the gate structure (110) having a gate corner (125). The transistor (100) also includes a drain-extended well (115) surrounded by the doped semiconductor substrate (105). The drain-extended well (115) has an opposite dopant type as the doped semiconductor substrate (105). The drain-extended well (115) also has a low-doped region (145) between high-doped regions (150), wherein an edge of the low-doped region (155) is substantially coincident with a perimeter (140) defined by the gate corner (125). Other embodiments of the present invention include a method of manufacturing a transistor (200) and an integrated circuit (300).

摘要翻译： 本发明在一个实施例中提供一种晶体管（100）。 晶体管（100）包括半导体衬底（105）上方的掺杂半导体衬底（105）和栅极结构（110），栅极结构（110）具有栅极拐角（125）。 晶体管（100）还包括由掺杂半导体衬底（105）围绕的漏极扩展阱（115）。 漏极扩展阱（115）具有与掺杂半导体衬底（105）相反的掺杂剂类型。 漏极扩展阱（115）还在高掺杂区域（150）之间具有低掺杂区域（145），其中低掺杂区域（155）的边缘基本上与由 门角（125）。 本发明的其他实施例包括制造晶体管（200）和集成电路（300）的方法。

公开(公告)号：US20050215018A1

公开(公告)日：2005-09-29

申请号：US11135544

申请日：2005-05-24

申请人： Pinghai Hao ,  Shanjen Pan ,  Sameer Pendharkar

发明人： Pinghai Hao ,  Shanjen Pan ,  Sameer Pendharkar

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/338 ,  H01L29/02 ,  H01L29/08 ,  H01L29/78 ,  H01L47/00

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/7833

摘要： A transistor can be fabricated to exhibit reduced channel hot carrier effects. According to one aspect of the present invention, a method for fabricating a transistor structure includes implanting a first dopant into a lightly doped drain (LDD) region to form a shallow region therein. The first dopant penetrates the substrate to a depth that is less than the LDD junction depth. A second dopant is implanted into the substrate beyond the LDD junction depth to form a source/drain region. The implantation of the second dopant overpowers a substantial portion of the first dopant to define a floating ring in the LDD region that mitigates channel hot carrier effects.

摘要翻译： 可以制造晶体管以显示减少的通道热载体效应。 根据本发明的一个方面，制造晶体管结构的方法包括将第一掺杂剂注入到轻掺杂漏极（LDD）区域中以在其中形成浅区域。 第一掺杂剂将衬底渗透至小于LDD结深度的深度。 将第二掺杂剂注入超过LDD结深度的衬底中以形成源/漏区。 第二掺杂剂的注入超过第一掺杂剂的大部分，以限定LDD区域中的浮动环，其缓和了通道热载流子效应。

公开(公告)号：US20050110081A1

公开(公告)日：2005-05-26

申请号：US10721567

申请日：2003-11-25

申请人： Sameer Pendharkar

发明人： Sameer Pendharkar

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/76 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/0653 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0692 ,  H01L29/42368 ,  H01L29/7835

摘要： A drain-extended metal-oxide-semiconductor transistor (40) with improved robustness in breakdown characteristics is disclosed. Field oxide isolation structures (29c) are disposed between the source region (30) and drain contact regions (32a, 32b, 32c) to break the channel region of the transistor into parallel sections. The gate electrode (35) extends over the multiple channel regions, and the underlying well (26) and thus the drift region (DFT) of the transistor extends along the full channel width. Channel stop doped regions (33) underlie the field oxide isolation structures (29c), and provide conductive paths for carriers during breakdown. Parasitic bipolar conduction, and damage due to that conduction, is therefore avoided.

摘要翻译： 公开了具有改善的击穿特性鲁棒性的漏极延伸金属氧化物半导体晶体管（40）。 场源氧化物隔离结构（29c）设置在源极区域（30）和漏极接触区域（32a，32b，32c）之间，以将晶体管的沟道区域断开成平行段。 栅极电极（35）在多个沟道区域上延伸，并且下面的阱（26）以及晶体管的漂移区域（DFT）沿整个沟道宽度延伸。 通道阻挡掺杂区域（33）位于场氧化物隔离结构（29c）的下面，并且在击穿期间为载体提供导电路径。 因此避免了寄生双极导电和由于导电导致的损坏。

公开(公告)号：US06211552B1

公开(公告)日：2001-04-03

申请号：US09320953

申请日：1999-05-27

申请人： Taylor R. Efland ,  Sameer Pendharkar ,  Dan M. Mosher ,  Peter Chia-cu Mei

发明人： Taylor R. Efland ,  Sameer Pendharkar ,  Dan M. Mosher ,  Peter Chia-cu Mei

IPC分类号： H01L2978

CPC分类号： H01L29/0847 ,  H01L29/0653 ,  H01L29/66659 ,  H01L29/7835

摘要： A RESURF LDMOS transistor (32) has a drain region including a first region (24) and a deep drain buffer region (34) surrounding the first region. The first region is more heavily doped than the deep drain buffer region. The deep drain buffer region improves the robustness of the transistor.

摘要翻译： RESURF LDMOS晶体管（32）具有包括围绕第一区域的第一区域（24）和深漏极缓冲区域（34）的漏极区域。 第一区域比深漏极缓冲区域更重掺杂。 深漏极缓冲区域提高了晶体管的鲁棒性。

公开(公告)号：US09806190B2

公开(公告)日：2017-10-31

申请号：US13282305

申请日：2011-10-26

申请人： Marie Denison ,  Philip L. Hower ,  Sameer Pendharkar

发明人： Marie Denison ,  Philip L. Hower ,  Sameer Pendharkar

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L27/12 ,  H01L29/10 ,  H01L29/861 ,  H01L27/06

CPC分类号： H01L29/7824 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/1087 ,  H01L29/7818 ,  H01L29/7835 ,  H01L29/861

摘要： An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) so that the drain or body region is coupled to the handle wafer through a p-n junction. An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) coupled to the handle wafer through a p-n junction, that is electrically isolated from the drain or body region. A process of forming an integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel).

公开(公告)号：US09293357B2

公开(公告)日：2016-03-22

申请号：US13540542

申请日：2012-07-02

申请人： Binghua Hu ,  Sameer Pendharkar ,  Guru Mathur ,  Takehito Tamura

发明人： Binghua Hu ,  Sameer Pendharkar ,  Guru Mathur ,  Takehito Tamura

IPC分类号： H01L29/49 ,  H01L21/762 ,  H01L29/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/283 ,  H01L21/3205

CPC分类号： H01L21/76224 ,  H01L21/02109 ,  H01L21/265 ,  H01L21/283 ,  H01L21/32055 ,  H01L21/76232 ,  H01L29/0619

摘要： The width of a heavily-doped sinker is substantially reduced by forming the heavily-doped sinker to lie in between a number of closely-spaced trench isolation structures, which have been formed in a semiconductor material. During drive-in, the closely-spaced trench isolation structures significantly limit the lateral diffusion.

摘要翻译： 通过形成重掺杂沉降片位于已形成于半导体材料中的多个紧密间隔的沟槽隔离结构之间，大大减小了重掺杂沉降片的宽度。 在进入期间，紧密间隔的沟槽隔离结构显着限制了横向扩散。

公开(公告)号：US09076760B2

公开(公告)日：2015-07-07

申请号：US13597439

申请日：2012-08-29

申请人： Binghua Hu ,  Pinghai Hao ,  Sameer Pendharkar

发明人： Binghua Hu ,  Pinghai Hao ,  Sameer Pendharkar

IPC分类号： G01R31/26 ,  H01L29/417 ,  H01L21/00 ,  H01L29/423 ,  H01L29/808 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L29/41725 ,  G06F2101/00 ,  G06F2201/00 ,  H01L21/00 ,  H01L29/0692 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/808

摘要： A junction field-effect transistor (JFET) includes a substrate having a first-type semiconductor surface including a topside surface, and a top gate of a second-type formed in the semiconductor surface. A first-type drain and a first-type source are formed on opposing sides of the top gate. A first deep trench isolation region has an inner first trench wall and an outer first trench wall surrounding the top gate, the drain and the source, and extends vertically to a deep trench depth from the topside surface. A second-type sinker formed in semiconductor surface extends laterally outside the outer first trench wall. The sinker extends vertically from the topside surface to a second-type deep portion which is both below the deep trench depth and laterally inside the inner first trench wall to provide a bottom gate.

摘要翻译： 结型场效应晶体管（JFET）包括具有包括顶侧表面的第一类型半导体表面的衬底和形成在半导体表面中的第二类型的顶栅。 第一型漏极和第一型源形成在顶栅的相对侧上。 第一深沟槽隔离区域具有围绕顶部栅极，漏极和源极的内部第一沟槽壁和外部第一沟槽壁，并且从顶侧表面垂直延伸到深沟槽深度。 形成在半导体表面中的第二类型沉降片在外部第一沟槽壁的外侧横向延伸。 沉降片从顶侧表面垂直延伸到第二类型深部，该深部位于深沟槽深度的下方并且在内部第一沟槽壁的横向内部以提供底部门。

公开(公告)号：US08853029B2

公开(公告)日：2014-10-07

申请号：US13188162

申请日：2011-07-21

申请人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin

发明人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC分类号： H01L29/7813 ,  H01L29/42368 ,  H01L29/66719 ,  H01L29/66734

摘要： An electronic device has a plurality of trenches formed in a semiconductor layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric having increased thickness at greater depth is located between the field plate section and the vertical drift region.

摘要翻译： 电子器件具有形成在半导体层中的多个沟槽。 垂直漂移区域位于沟槽之间和相邻的沟槽之间。 电极位于每个沟槽内，电极具有栅电极部分和场板部分。 在场板部分和垂直漂移区域之间设置具有较大深度的厚度增加的分级场板电介质。