公开(公告)号：US06211552B1

公开(公告)日：2001-04-03

申请号：US09320953

申请日：1999-05-27

申请人： Taylor R. Efland ,  Sameer Pendharkar ,  Dan M. Mosher ,  Peter Chia-cu Mei

发明人： Taylor R. Efland ,  Sameer Pendharkar ,  Dan M. Mosher ,  Peter Chia-cu Mei

IPC分类号： H01L2978

CPC分类号： H01L29/0847 ,  H01L29/0653 ,  H01L29/66659 ,  H01L29/7835

摘要： A RESURF LDMOS transistor (32) has a drain region including a first region (24) and a deep drain buffer region (34) surrounding the first region. The first region is more heavily doped than the deep drain buffer region. The deep drain buffer region improves the robustness of the transistor.

摘要翻译： RESURF LDMOS晶体管（32）具有包括围绕第一区域的第一区域（24）和深漏极缓冲区域（34）的漏极区域。 第一区域比深漏极缓冲区域更重掺杂。 深漏极缓冲区域提高了晶体管的鲁棒性。

公开(公告)号：US07514329B2

公开(公告)日：2009-04-07

申请号：US11325165

申请日：2006-01-04

申请人： Sameer Pendharkar ,  Ramanathan Ramani ,  Taylor R. Efland

发明人： Sameer Pendharkar ,  Ramanathan Ramani ,  Taylor R. Efland

IPC分类号： H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7835

摘要： Extended-drain MOS transistor devices and fabrication methods are provided, in which a drift region of a first conductivity type is formed between a drain of the first conductivity type and a channel. The drift region comprises first and second portions, the first portion extending partially under a gate structure between the channel and the second portion, and the second portion extending laterally between the first portion and the drain, wherein the first portion of the drift region has a concentration of first type dopants higher than the second portion.

摘要翻译： 提供了扩大漏极MOS晶体管器件和制造方法，其中在第一导电类型的漏极和沟道之间形成第一导电类型的漂移区域。 所述漂移区域包括第一和第二部分，所述第一部分部分地在所述通道和所述第二部分之间的栅极结构下方延伸，并且所述第二部分在所述第一部分和所述漏极之间横向延伸，其中所述漂移区域的所述第一部分具有 第一种掺杂剂的浓度高于第二部分。

公开(公告)号：US06424005B1

公开(公告)日：2002-07-23

申请号：US09205657

申请日：1998-12-03

申请人： Chin-Yu Tsai ,  Taylor R. Efland ,  Sameer Pendharkar ,  John P. Erdeljac ,  Jozef Mitros ,  Jeffrey P. Smith ,  Louis N. Hutter

发明人： Chin-Yu Tsai ,  Taylor R. Efland ,  Sameer Pendharkar ,  John P. Erdeljac ,  Jozef Mitros ,  Jeffrey P. Smith ,  Louis N. Hutter

IPC分类号： H01L31113

CPC分类号： H01L29/66689 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/7816

摘要： An LDMOS device (10, 20, 50, 60) that is made with minimal feature size fabrication methods, but overcomes potential problems of misaligned Dwells (13). The Dwell (13) is slightly overstated so that its n-type dopant is implanted past the source edge of the gate region (18), which permits the n-type region of the Dwell to diffuse under the gate region (18) an sufficient distance to eliminate misalignment effects.

摘要翻译： LDMOS器件（10,20,50,60）采用最小的特征尺寸制造方法制造，但克服了不对准Dwells的潜在问题（13）。 驻留（13）略微夸大，使得其n型掺杂剂被注入超过栅极区域（18）的源极边缘，这允许Dwell的n型区域在栅极区域（18）下扩散到足够的 距离消除不对准效应。

公开(公告)号：US07514292B2

公开(公告)日：2009-04-07

申请号：US11539486

申请日：2006-10-06

申请人： Taylor R Efland ,  Milton L Buschbom ,  Sameer Pendharkar

发明人： Taylor R Efland ,  Milton L Buschbom ,  Sameer Pendharkar

IPC分类号： H01L21/00

CPC分类号： H01L24/05 ,  H01L23/5286 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/0518 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48764 ,  H01L2224/48769 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48864 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/15724 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/48869

摘要： An integrated circuit (IC) chip, mounted on a leadframe, has a network of power distribution lines deposited on the surface of the chip so that these lines are located over active components of the IC, connected vertically by metal-filled vias to selected active components below the lines, and also by conductors to segments of the leadframe. Furthermore, the lines are fabricated with a sheet resistance of less than 1.5 mΩ/· and the majority of the lines is patterned as straight lines between the vias and the conductors, respectively.

摘要翻译： 安装在引线框架上的集成电路（IC）芯片具有沉积在芯片表面上的配电线网络，使得这些线路位于IC的有源元件上方，通过金属填充的通孔垂直连接到选定的有源 线路下方的组件，以及引线框架的导体。 此外，线路的薄层电阻小于1.5mOmega /。 并且大多数线分别被图案化为通孔和导体之间的直线。

公开(公告)号：US07135759B2

公开(公告)日：2006-11-14

申请号：US10039663

申请日：2001-10-22

申请人： Taylor R. Efland ,  Milton L. Buschbom ,  Sameer Pendharkar

发明人： Taylor R. Efland ,  Milton L. Buschbom ,  Sameer Pendharkar

IPC分类号： H01L23/495

CPC分类号： H01L24/05 ,  H01L23/5286 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/0518 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48764 ,  H01L2224/48769 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48864 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/15724 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/48869

摘要： An integrated circuit (IC) chip, mounted on a leadframe, has a network of power distribution lines deposited on the surface of the chip so that these lines are located over active components of the IC, connected vertically by metal-filled vias to selected active components below the lines, and also by conductors to segments of the leadframe. Furthermore, the lines are fabricated with a sheet resistance of less than 1.5 mΩ/□ and the majority of the lines is patterned as straight lines between the vias and the conductors, respectively.

摘要翻译： 安装在引线框架上的集成电路（IC）芯片具有沉积在芯片表面上的配电线网络，使得这些线路位于IC的有源元件上方，通过金属填充的通孔垂直连接到选定的有源 线路下方的组件，以及引线框架的导体。 此外，线路的薄层电阻小于1.5mOmega /□，并且大部分线路分别图案化为通孔和导体之间的直线。

公开(公告)号：US07238986B2

公开(公告)日：2007-07-03

申请号：US10837918

申请日：2004-05-03

申请人： Sameer Pendharkar ,  Ramanathan Ramani ,  Taylor R. Efland

发明人： Sameer Pendharkar ,  Ramanathan Ramani ,  Taylor R. Efland

IPC分类号： H01L29/76

CPC分类号： H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7835

摘要： Extended-drain MOS transistor devices and fabrication methods are provided, in which a drift region of a first conductivity type is formed between a drain of the first conductivity type and a channel. The drift region comprises first and second portions, the first portion extending partially under a gate structure between the channel and the second portion, and the second portion extending laterally between the first portion and the drain, wherein the first portion of the drift region has a concentration of first type dopants higher than the second portion.

摘要翻译： 提供了扩大漏极MOS晶体管器件和制造方法，其中在第一导电类型的漏极和沟道之间形成第一导电类型的漂移区域。 所述漂移区域包括第一和第二部分，所述第一部分部分地在所述通道和所述第二部分之间的栅极结构下方延伸，并且所述第二部分在所述第一部分和所述漏极之间横向延伸，其中所述漂移区域的所述第一部分具有 第一种掺杂剂的浓度高于第二部分。

公开(公告)号：US07195965B2

公开(公告)日：2007-03-27

申请号：US10302256

申请日：2002-11-22

申请人： John Lin ,  Philip L. Hower ,  Taylor R. Efland ,  Sameer Pendharkar ,  Vladimir Bolkhovsky

发明人： John Lin ,  Philip L. Hower ,  Taylor R. Efland ,  Sameer Pendharkar ,  Vladimir Bolkhovsky

IPC分类号： H01L21/8248

CPC分类号： H01L29/7816 ,  H01L21/266 ,  H01L29/0615 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66674 ,  H01L29/7322 ,  H01L29/8611

摘要： The concept of the present invention describes a semiconductor device with a junction 504 between a lightly doped region 501 and a heavily doped region 502, wherein the junction has an elongated portion 504a and curved portions 504b. The doping concentration of the lightly doped region is configured so that it exhibits higher resistivity in the proximity 510 of the curved portion by an amount suitable to lower the electric field strength during device operation and thus to offset the increased field strength caused by the curved portion. As a consequence, the device breakdown voltage in the curved junction portion becomes equal to or greater than the breakdown voltage in the linear portion.

摘要翻译： 本发明的概念描述了在轻掺杂区域501和重掺杂区域502之间具有结504的半导体器件，其中该接合部具有细长部分504a和弯曲部分504b。 轻掺杂区域的掺杂浓度被配置为使得其在弯曲部分的接近510处表现出较高的电阻率，其量适于在器件操作期间降低电场强度，并因此抵消由弯曲部分引起的增加的场强 。 结果，弯曲接合部中的器件击穿电压变得等于或大于直线部分中的击穿电压。

公开(公告)号：US07045903B2

公开(公告)日：2006-05-16

申请号：US09917419

申请日：2001-07-30

申请人： Taylor R. Efland ,  Sameer Pendharkar

发明人： Taylor R. Efland ,  Sameer Pendharkar

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/48 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/5286 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/0518 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/4554 ,  H01L2224/45669 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4845 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48769 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01037 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/01007 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2224/48869 ,  H01L2924/20755 ,  H01L2924/00015 ,  H01L2924/2075

摘要： A semiconductor integrated circuit comprises contact pads located over active components, which are positioned to minimize the distance for power delivery between a selected pad and one or more corresponding active components, to which the power is to be delivered. This minimum distance further enhances dissipation of thermal energy released by the active components.More specifically, a semiconductor integrated circuit comprises a laterally organized power transistor, an array of power supply contact pads distributed over the transistor, means for providing a distributed, predominantly vertical current flow from the contact pads to the transistor, and means for connecting a power source to each of the contact pads. Positioning the power supply contact pads directly over the active power transistor further saves precious silicon real estate area. The means for vertical current flow include contact pads made of a stack of metal layers comprising refractory metals for adhesion, copper and nickel as stress-absorbing metals, and gold or palladium as bondable and solderable outermost metals. The means for connecting a power source include wire bonding and solder ball interconnection.

公开(公告)号：US06395593B1

公开(公告)日：2002-05-28

申请号：US09550746

申请日：2000-04-17

申请人： Sameer Pendharkar ,  Taylor R. Efland

发明人： Sameer Pendharkar ,  Taylor R. Efland

IPC分类号： H01L218238

CPC分类号： H01L29/7835 ,  H01L21/761 ,  H01L29/1087

摘要： A method of minimizing parasitics in an MOS device caused by the formation of a bipolar transistor within the MOS devices and the device, primarily for a polyphase bridge circuit. For the low side device, a substrate of a first conductivity type is provided having a first buried layer of opposite conductivity type thereon. A second buried layer of the first conductivity type is formed over the first buried layer and a further layer of the first conductivity type is formed over the second buried layer. A sinker extending through the further layer to the first buried layer is formed to isolate the second buried layer and the further layer from the substrate. Formation of an MOS device in the further layer including source, drain and gate regions is completed and the sinker is connected to a source terminal of the device. The second buried layer is formed either by coimplanting a p-type dopant and an n-type dopant with one of the dopant having a higher diffusion rate than the other or by implanting and diffusing one of the two dopants first to form one layer and then implanting and diffusing the other dopant to form the second layer. The preferred dopants are boron as the p-type dopant and antimony as the n-type dopant.

摘要翻译： 一种使MOS器件中的寄生效应最小化的方法，其由MOS器件和器件内的双极晶体管形成，主要用于多相桥式电路。 对于低侧装置，提供具有第一导电类型的衬底，其上具有相反导电类型的第一掩埋层。 第一导电类型的第二掩埋层形成在第一掩埋层上，并且第二导电类型的另一层形成在第二掩埋层上。 形成了延伸穿过另一层到第一掩埋层的沉降片，以将第二掩埋层和另外的层与衬底隔离。 在包括源极，漏极和栅极区域的另外的层中形成MOS器件，并且沉降片连接到器件的源极端子。 第二掩埋层通过将p型掺杂剂和n型掺杂剂与其中一种具有比另一种扩散速率更高的扩散速率的掺杂剂或通过首先注入和扩散两种掺杂剂之一形成一层形成，然后 植入和扩散另一种掺杂剂以形成第二层。 优选的掺杂剂是作为p型掺杂剂的硼和作为n型掺杂剂的锑。

公开(公告)号：US07888196B2

公开(公告)日：2011-02-15

申请号：US12345072

申请日：2008-12-29

申请人： Seetharaman Sridhar ,  Sameer Pendharkar ,  Dan M. Mosher

发明人： Seetharaman Sridhar ,  Sameer Pendharkar ,  Dan M. Mosher

IPC分类号： H01L21/8238

CPC分类号： H01L21/823462 ,  H01L21/76229 ,  H01L21/823481 ,  H01L21/823857 ,  H01L21/823878

摘要： A method of fabricating an integrated circuit (IC) including a first plurality of MOS transistors having a first gate dielectric having a first thickness in first regions, and a second plurality of MOS transistors having a second gate dielectric having a second thickness in second regions, wherein the first thickness

摘要翻译： 一种制造集成电路（IC）的方法，所述集成电路（IC）包括第一多个MOS晶体管，所述第一多个MOS晶体管具有在第一区域中具有第一厚度的第一栅极电介质，以及第二多个MOS晶体管， 其中所述第一厚度<所述第二厚度。 提供具有半导体表面的衬底。 具有厚度为nlE的焊盘电介质层;在包括第二区域的半导体表面上形成第二厚度，其中焊盘介电层为第二栅极电介质提供第二厚度的至少一部分。 在包括第二区域的半导体表面上形成硬掩模层。 通过蚀刻通过焊盘介电层和半导体表面的一部分形成多个沟槽隔离区域。 多个沟槽隔离区域填充有介电填充材料以形成沟槽隔离区域，然后去除硬掩模层。 在第二栅极电介质上形成图案化的栅极电极层，其中所述图案化的栅极电极层在至少一个沟槽隔离区域的表面上延伸。 然后完成第一和第二区域中的MOS晶体管的制造。