公开(公告)号：US10032937B2

公开(公告)日：2018-07-24

申请号：US15349162

申请日：2016-11-11

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Ali Salih ,  Gordon M. Grivna ,  Daniel R. Heuttl ,  Osamu Ishimaru ,  Thomas Keena ,  Masafumi Uehara

IPC: H01L29/49 ,  H01L29/861 ,  H01L29/06 ,  H01L29/41 ,  H01L29/45 ,  H01L29/40 ,  H01L29/66 ,  H01L27/08

Abstract: A semiconductor device structure includes a region of semiconductor material with a first major surface and an opposing second major surface. A contact structure is disposed in a first portion of the region of semiconductor material and includes a tub structure extending from adjacent a first portion of the first major surface. A plurality of structures comprising portions of the region of semiconductor material extend outward from a lower surface of the tub structure. In some embodiments, the plurality of structures comprises a plurality of free-standing structures. A conductive material is disposed within the tub structure and laterally surrounding the plurality of structures. In one embodiment, the contact structure facilitates the fabrication of a monolithic series switching diode structure having a low-resistance substrate contact.

公开(公告)号：US09966462B2

公开(公告)日：2018-05-08

申请号：US15208466

申请日：2016-07-12

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Woochul Jeon ,  Chun-Li Liu ,  Ali Salih

IPC: H01L29/15 ,  H01L29/778 ,  H01L29/20 ,  H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L27/088 ,  H01L29/16 ,  H01L23/495

CPC classification number: H01L29/778 ,  H01L23/4952 ,  H01L23/49537 ,  H01L23/585 ,  H01L27/0883 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1066 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/42316

Abstract: Implementations of semiconductor devices may include: a plurality of drain fingers and a plurality of source fingers interdigitated with one another; at least one gate; and at gate bus formed to completely surround the plurality of drain fingers and the plurality of source fingers; wherein the gate bus is mechanically and electrically coupled to the at least one gate.

公开(公告)号：US09947654B2

公开(公告)日：2018-04-17

申请号：US15260185

申请日：2016-09-08

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Woochul Jeon ,  Ali Salih

IPC: H01L29/49 ,  H01L27/06 ,  H01L23/528 ,  H01L49/02 ,  H01L29/40 ,  H01L27/088 ,  H01L29/417 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/7787 ,  H01L27/0883 ,  H01L28/40 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7786

Abstract: In an aspect, a cascode circuit can include a high-side transistor and a low-side transistor. The source of the high-side transistor can be coupled to the drain of the low-side transistor; and the gate of the high-side transistor can be coupled to each of the source and the gate of the low-side transistor. In another aspect, an electronic device can include a high-side transistor, a low-side transistor, and a field electrode. The low-side transistor can include a drain region coupled to the source electrode of the high-side transistor. The field electrode can overlie and be capacitively coupled to a channel layer of the high-side transistor, wherein the field electrode is configured to be at a voltage between the voltages of the high-side and low-side power supply terminals.

公开(公告)号：US20180005927A1

公开(公告)日：2018-01-04

申请号：US15690773

申请日：2017-08-30

Applicant: Semiconductor Components Industries, LLC

Inventor： Chun-Li Liu ,  Ali Salih ,  Balaji Padmanabhan ,  Mingjiao Liu

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/498 ,  H01L25/18 ,  H01L23/373 ,  H01L29/20 ,  H01L29/16

CPC classification number: H01L23/49575 ,  H01L23/3735 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/18 ,  H01L29/16 ,  H01L29/2003 ,  H01L2224/32145 ,  H01L2224/37099 ,  H01L2224/40105 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48145 ,  H01L2224/48245 ,  H01L2224/49112 ,  H01L2224/49176 ,  H01L2224/49177 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/1306 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/85399

Abstract: A semiconductor component includes a support having a lead integrally formed thereto. An insulated metal substrate is mounted to a surface of the support and a semiconductor chip is mounted to the insulated metal substrate. A III-N based semiconductor chip is mounted to the insulated metal substrate, where the III-N based semiconductor chip has a gate bond pad, a drain bond pad, and a source bond pad. A silicon based semiconductor chip is mounted to the III-N based semiconductor chip. In accordance with an embodiment the silicon based semiconductor chip includes a device having a gate bond pad, a drain bond pad, and a source bond pad. The drain bond pad of the III-N based semiconductor chip may be bonded to the substrate or to a lead. In accordance with another embodiment, the silicon based semiconductor chip is a diode.

公开(公告)号：US09780019B2

公开(公告)日：2017-10-03

申请号：US15207626

申请日：2016-07-12

Applicant: Semiconductor Components Industries, LLC

Inventor： Chun-Li Liu ,  Ali Salih ,  Balaji Padmanabhan ,  Mingjiao Liu

IPC: H01L23/495 ,  H01L25/18 ,  H01L23/00 ,  H01L23/498 ,  H01L29/20 ,  H01L29/16 ,  H01L23/373

CPC classification number: H01L23/49575 ,  H01L23/3735 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/18 ,  H01L29/16 ,  H01L29/2003 ,  H01L2224/37099 ,  H01L2224/40105 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48145 ,  H01L2224/48245 ,  H01L2224/49112 ,  H01L2224/49176 ,  H01L2224/49177 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/1306 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/85399

Abstract: A semiconductor component includes a support having a lead integrally formed thereto. An insulated metal substrate is mounted to a surface of the support and a semiconductor chip is mounted to the insulated metal substrate. A III-N based semiconductor chip is mounted to the insulated metal substrate, where the III-N based semiconductor chip has a gate bond pad, a drain bond pad, and a source bond pad. A silicon based semiconductor chip is mounted to the III-N based semiconductor chip. In accordance with an embodiment the silicon based semiconductor chip includes a device having a gate bond pad, a drain bond pad, and a source bond pad. The drain bond pad of the III-N based semiconductor chip may be bonded to the substrate or to a lead. In accordance with another embodiment, the silicon based semiconductor chip is a diode.

公开(公告)号：US20170221752A1

公开(公告)日：2017-08-03

申请号：US15487517

申请日：2017-04-14

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chun-Li Liu ,  Balaji Padmanabhan ,  Ali Salih ,  Peter Moens

IPC: H01L21/76 ,  H01L21/763 ,  H01L21/762 ,  H01L29/20 ,  H01L29/06

CPC classification number: H01L29/7827 ,  H01L21/743 ,  H01L21/746 ,  H01L21/7605 ,  H01L21/76224 ,  H01L21/763 ,  H01L21/76898 ,  H01L29/0607 ,  H01L29/0649 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/66318 ,  H01L29/66462 ,  H01L29/66666 ,  H01L29/7786

Abstract: In accordance with an embodiment, a semiconductor component includes a plurality of layers of compound semiconductor material over a body of semiconductor material and first and second filled trenches extending into the plurality of layers of compound semiconductor material. The first trench has first and second sidewalls and a floor and a first dielectric liner over the first and second sidewalls and the second trench has first and second sidewalls and a floor and second dielectric liner over the first and second sidewalls of the second trench.

公开(公告)号：US20170025335A1

公开(公告)日：2017-01-26

申请号：US15202765

申请日：2016-07-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chun-Li Liu ,  Ali Salih ,  Balaji Padmanabhan ,  Mingjiao Liu

IPC: H01L23/495 ,  H01L23/00 ,  H01L29/45

CPC classification number: H01L23/49575 ,  H01L23/3735 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/73 ,  H01L25/072 ,  H01L29/2003 ,  H01L33/62 ,  H01L2224/40 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/49111 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2224/37099

Abstract: In accordance with an embodiment, a semiconductor component is provided that includes a leadframe having a device receiving area, one or more leadframe leads and at least one insulated metal substrate bonded to a first portion of the device receiving area. A first semiconductor device is mounted to a first insulated metal substrate, the first semiconductor device configured from a III-N semiconductor material. A first electrical interconnect is coupled between the first current carrying terminal of the first semiconductor device and a second portion of the die receiving area. In accordance with another embodiment, method includes providing a first semiconductor chip comprising a III-N semiconductor substrate material and a second semiconductor chip comprising a silicon based semiconductor substrate. The first semiconductor chip is mounted on a first substrate and the second semiconductor chip on a second substrate. The first semiconductor chip is electrically coupled to the second semiconductor chip.

Abstract translation: 根据实施例，提供了半导体部件，其包括具有器件接收区域的引线框架，一个或多个引线框架引线以及结合到器件接收区域的第一部分的至少一个绝缘金属衬底。 第一半导体器件安装到第一绝缘金属衬底，第一半导体器件由III-N半导体材料构成。 第一电互连耦合在第一半导体器件的第一载流端子和管芯接收区域的第二部分之间。 根据另一实施例，方法包括提供包括III-N半导体衬底材料的第一半导体芯片和包括硅基半导体衬底的第二半导体芯片。 第一半导体芯片安装在第一基板上，第二半导体芯片安装在第二基板上。 第一半导体芯片电耦合到第二半导体芯片。

公开(公告)号：US09391135B1

公开(公告)日：2016-07-12

申请号：US14665175

申请日：2015-03-23

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. Grivna ,  Ali Salih

IPC: H01L29/06 ,  H01L29/739 ,  H01L29/66

CPC classification number: H01L29/66333 ,  H01L21/265 ,  H01L21/3043 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/76224 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/41766 ,  H01L29/66348 ,  H01L29/7397

Abstract: In one embodiment, an IGBT is formed to include a plurality of termination trenches in a termination region of the IGBT. An embodiment may include that one end of one or more termination trenches may be exposed on one surface of the semiconductor device.

Abstract translation: 在一个实施例中，IGBT形成为在IGBT的端接区域中包括多个端接沟槽。 一个实施例可以包括一个或多个终止沟槽的一端可以暴露在半导体器件的一个表面上。

公开(公告)号：US09299776B2

公开(公告)日：2016-03-29

申请号：US14297204

申请日：2014-06-05

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. Grivna ,  Zia Hossain ,  Ali Salih

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/768 ,  H01L21/762

CPC classification number: H01L21/76205 ,  H01L21/76816 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

Abstract: In an embodiment, a method of forming a semiconductor may include forming a plurality of active trenches and forming a termination trench substantially surrounding an outer periphery of the plurality of active trenches. The method may also include forming at least one active trench of the plurality of active trenches having corners linking trench ends to sides of active trenches wherein each active trench of the plurality of active trenches has a first profile along the first length and a second profile at or near the trench ends; and forming a termination trench substantially surrounding an outer periphery of the plurality of active trenches and having a second profile wherein one of the first profile or the second profile includes a non-linear shape.

Abstract translation: 在一个实施例中，形成半导体的方法可以包括形成多个有源沟槽并且形成基本上围绕多个有源沟槽的外周边的端接沟槽。 该方法还可以包括形成多个有源沟槽中的至少一个有源沟槽，其具有将沟槽端部连接到有源沟槽侧面的角，其中多个有源沟槽中的每个有源沟槽具有沿着第一长度的第一轮廓， 或在沟槽末端附近; 以及形成基本上围绕所述多个有源沟槽的外周边的终端沟槽，并且具有第二形状，其中所述第一形状或所述第二形状中的一个包括非线性形状。

公开(公告)号：US09129889B2

公开(公告)日：2015-09-08

申请号：US14203299

申请日：2014-03-10

Applicant: Semiconductor Components Industries, LLC

Inventor： Balaji Padmanabhan ,  John Michael Parsey, Jr. ,  Ali Salih ,  Prasad Venkatraman

IPC: H01L29/00 ,  H01L29/20 ,  H01L29/778 ,  H01L29/40 ,  H01L29/66 ,  H01L29/04 ,  H01L29/06 ,  H01L29/205 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7783 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/41791 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7789 ,  H01L29/785 ,  H01L29/872

Abstract: In one embodiment, Group III-nitride materials are used to form a semiconductor device. A fin structure is formed in the Group III-nitride material, and a gate structure, source electrodes and drain electrodes are formed in spaced relationship to the fin structure. The fin structure provides both polar and semi-polar 2DEG regions. In one embodiment, the gate structure is configured to control current flow in the polar 2DEG region. Shield conductor layers are included above the gate structure and in spaced relationship with drain regions of the semiconductor device.

Abstract translation: 在一个实施例中，III族氮化物材料用于形成半导体器件。 在III族氮化物材料中形成翅片结构，并且栅极结构，源电极和漏电极形成为与翅片结构间隔开的关系。 鳍结构提供极性和半极性2DEG区域。 在一个实施例中，门结构被配置为控制极地2DEG区域中的电流。 屏蔽导体层包括在栅极结构之上并与半导体器件的漏极区间隔开。