公开(公告)号：US09735180B2

公开(公告)日：2017-08-15

申请号：US15159131

申请日：2016-05-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hajime Kimura ,  Atsushi Umezaki ,  Shunpei Yamazaki

IPC: H01L31/107 ,  H01L27/12 ,  G02F1/1334 ,  G02F1/1368 ,  G02F1/1333 ,  G02F1/1343 ,  G02F1/1362 ,  G09G3/20 ,  G09G3/36 ,  H01L29/24 ,  H01L29/786 ,  H01L21/8234

CPC classification number: H01L27/124 ,  G02F1/133345 ,  G02F1/1334 ,  G02F1/134309 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  G02F2001/13345 ,  G09G3/2007 ,  G09G3/36 ,  G09G2300/0426 ,  G09G2310/0289 ,  G09G2310/08 ,  G09G2320/0252 ,  G09G2320/0257 ,  G09G2330/021 ,  H01L21/823412 ,  H01L27/1225 ,  H01L27/127 ,  H01L29/247 ,  H01L29/786 ,  H01L29/78606 ,  H01L29/78693 ,  H01L29/78696

Abstract: An object is to improve the drive capability of a semiconductor device. The semiconductor device includes a first transistor and a second transistor. A first terminal of the first transistor is electrically connected to a first wiring. A second terminal of the first transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to a third wiring. A first terminal of the second transistor is electrically connected to the third wiring. A second terminal of the second transistor is electrically connected to a gate of the first transistor. A channel region is formed using an oxide semiconductor layer in each of the first transistor and the second transistor. The off-state current of each of the first transistor and the second transistor per channel width of 1 μm is 1 aA or less.

公开(公告)号：US09552761B2

公开(公告)日：2017-01-24

申请号：US14714395

申请日：2015-05-18

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hajime Kimura ,  Atsushi Umezaki

IPC: G09G3/20 ,  G09G3/36

CPC classification number: G09G3/3648 ,  G09G3/2096 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2300/0814 ,  G09G2300/0819 ,  G09G2320/0209 ,  G09G2320/0223 ,  G09G2320/043

Abstract: A semiconductor device where delay or distortion of a signal output to a gate signal line in a selection period is reduced is provided. The semiconductor device includes a gate signal line, a first and second gate driver circuits which output a selection signal and a non-selection signal to the gate signal line, and pixels electrically connected to the gate signal line and supplied with the two signals. In a period during which the gate signal line is selected, both the first and second gate driver circuits output the selection signal to the gate signal line. In a period during which the gate signal line is not selected, one of the first and second gate driver circuits outputs the non-selection signal to the gate signal line, and the other gate driver circuit outputs neither the selection signal nor the non-selection signal to the gate signal line.

Abstract translation: 提供了在选择期间输出到栅极信号线的信号的延迟或失真减小的半导体器件。 半导体器件包括栅极信号线，向栅极信号线输出选择信号和非选择信号的第一和第二栅极驱动器电路，以及电连接到栅极信号线并被提供有两个信号的像素。 在选择栅极信号线的期间，第一和第二栅极驱动电路都将选择信号输出到栅极信号线。 在没有选择栅极信号线的期间，第一和第二栅极驱动电路中的一个将非选择信号输出到栅极信号线，另一个栅极驱动电路既不输出选择信号也不输出非选择信号 信号到门信号线。

公开(公告)号：US09536903B2

公开(公告)日：2017-01-03

申请号：US14548365

申请日：2014-11-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki ,  Hiroyuki Miyake

IPC: G09G3/36 ,  H01L27/12 ,  G11C19/28

CPC classification number: H01L27/124 ,  G09G3/2092 ,  G09G3/3266 ,  G09G3/3674 ,  G09G3/3677 ,  G09G2300/0809 ,  G09G2310/0205 ,  G09G2310/0248 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0291 ,  G09G2310/061 ,  G09G2320/0646 ,  G09G2320/0666 ,  G11C19/28 ,  H01L27/0207 ,  H01L27/1222 ,  H01L27/1225

Abstract: To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction in power consumption of a display device, and to achieve increase in size and high definition of the display device. A gate electrode of a transistor which easily deteriorates is connected to a wiring to which a high potential is supplied through a first switching transistor and a wiring to which a low potential is supplied through a second switching transistor; a clock signal is input to a gate electrode of the first switching transistor; and an inverted clock signal is input to a gate electrode of the second switching transistor. Thus, the high potential and the low potential are alternately applied to the gate electrode of the transistor which easily deteriorates.

Abstract translation: 为了抑制晶体管的阈值电压的波动，为了减少显示面板和驱动器IC的连接数量，为了实现显示装置的功耗的降低，并且实现显示装置的尺寸和高清晰度的增加 。 容易恶化的晶体管的栅电极通过第一开关晶体管和通过第二开关晶体管供给低电位的布线而连接到提供高电位的布线; 时钟信号被输入到第一开关晶体管的栅电极; 并且反相时钟信号被输入到第二开关晶体管的栅电极。 因此，高电位和低电位交替施加到容易劣化的晶体管的栅电极。

公开(公告)号：US09432016B2

公开(公告)日：2016-08-30

申请号：US14594256

申请日：2015-01-12

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Atsushi Umezaki

IPC: H03B1/00 ,  H03K3/00 ,  H03K17/687 ,  H01L27/12 ,  G09G3/14 ,  G09G3/32 ,  G09G3/36 ,  H01L29/786

CPC classification number: H01L27/1255 ,  G09G3/14 ,  G09G3/32 ,  G09G3/36 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2330/021 ,  G11C19/00 ,  H01L29/7869 ,  H03B1/00 ,  H03K3/00 ,  H03K17/6871

Abstract: Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

公开(公告)号：US09406699B2

公开(公告)日：2016-08-02

申请号：US14143535

申请日：2013-12-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G11C19/00 ,  H01L27/12 ,  G02F1/1362 ,  G09G3/20 ,  G09G3/32 ,  G09G3/36 ,  G11C19/28 ,  H03K19/003 ,  H03K3/356

CPC classification number: H01L27/124 ,  G02F1/13624 ,  G09G3/20 ,  G09G3/325 ,  G09G3/3258 ,  G09G3/3266 ,  G09G3/3674 ,  G09G3/3696 ,  G09G2300/0408 ,  G09G2300/0809 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0297 ,  G09G2310/08 ,  G09G2330/021 ,  G11C19/28 ,  H01L27/1214 ,  H03K3/356 ,  H03K3/356104 ,  H03K19/00369

Abstract: An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

Abstract translation: 本发明的目的是提供一种能够抑制每个晶体管的特性劣化而不会发生不稳定操作的半导体器件。 在非选择期间，晶体管以规则的间隔导通，使得电源电位被提供给移位寄存器电路的输出端。 电源电位通过晶体管提供给移位寄存器电路的输出端。 由于在非选择期间晶体管不总是导通，所以抑制了晶体管的阈值电压的偏移。 此外，电源电位以规则的间隔通过晶体管提供给移位寄存器电路的输出端。 因此，移位寄存器电路可以抑制在输出端子中产生的噪声。

公开(公告)号：US09349757B2

公开(公告)日：2016-05-24

申请号：US14887517

申请日：2015-10-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hajime Kimura ,  Atsushi Umezaki ,  Shunpei Yamazaki

IPC: H01L31/107 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/124 ,  G02F1/133345 ,  G02F1/1334 ,  G02F1/134309 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  G02F2001/13345 ,  G09G3/2007 ,  G09G3/36 ,  G09G2300/0426 ,  G09G2310/0289 ,  G09G2310/08 ,  G09G2320/0252 ,  G09G2320/0257 ,  G09G2330/021 ,  H01L21/823412 ,  H01L27/1225 ,  H01L27/127 ,  H01L29/247 ,  H01L29/786 ,  H01L29/78606 ,  H01L29/78693 ,  H01L29/78696

Abstract: An object is to improve the drive capability of a semiconductor device. The semiconductor device includes a first transistor and a second transistor. A first terminal of the first transistor is electrically connected to a first wiring. A second terminal of the first transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to a third wiring. A first terminal of the second transistor is electrically connected to the third wiring. A second terminal of the second transistor is electrically connected to a gate of the first transistor. A channel region is formed using an oxide semiconductor layer in each of the first transistor and the second transistor. The off-state current of each of the first transistor and the second transistor per channel width of 1 μm is 1 aA or less.

公开(公告)号：US09335599B2

公开(公告)日：2016-05-10

申请号：US14934243

申请日：2015-11-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G09G3/36 ,  G02F1/1362 ,  H01L27/12 ,  H01L29/786 ,  H01L29/24

CPC classification number: G02F1/136286 ,  G02F1/13306 ,  G02F1/133753 ,  G02F1/13452 ,  G02F1/136213 ,  G02F1/1368 ,  G02F1/1393 ,  G02F2001/133622 ,  G02F2202/103 ,  G09G3/342 ,  G09G3/3655 ,  G09G3/3674 ,  G09G3/3677 ,  G09G3/3685 ,  G09G2300/0426 ,  G09G2300/0452 ,  G09G2310/024 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0252 ,  G09G2330/021 ,  G11C19/28 ,  H01L21/67167 ,  H01L27/06 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/15 ,  H01L27/156 ,  H01L27/3211 ,  H01L27/3213 ,  H01L27/3216 ,  H01L27/3248 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3265 ,  H01L27/3276 ,  H01L29/247 ,  H01L29/78693 ,  H01L51/5246 ,  H01L51/56 ,  H01L2251/5307 ,  H01L2251/5315 ,  H01L2251/5323

Abstract: A first transistor, a second transistor, a third transistor, a fourth transistor are provided. In the first transistor, a first terminal is electrically connected to a first wiring; a second terminal is electrically connected to a gate terminal of the second transistor; a gate terminal is electrically connected to a fifth wiring. In the second transistor, a first terminal is electrically connected to a third wiring; a second terminal is electrically connected to a sixth wiring. In the third transistor, a first terminal is electrically connected to a second wiring; a second terminal is electrically connected to the gate terminal of the second transistor; a gate terminal is electrically connected to a fourth wiring. In the fourth transistor, a first terminal is electrically connected to the second wiring; a second terminal is electrically connected to the sixth wiring; a gate terminal is connected to the fourth wiring.

公开(公告)号：US20150243678A1

公开(公告)日：2015-08-27

申请号：US14623193

申请日：2015-02-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: H01L27/12 ,  H01L29/10 ,  H01L23/538 ,  G02F1/1337 ,  H01L27/32 ,  G02F1/1368 ,  G02F1/1335 ,  H01L29/786 ,  H01L27/15

CPC classification number: H01L27/124 ,  G02F1/13306 ,  G09G3/20 ,  G09G3/3266 ,  G09G3/3674 ,  G09G3/3677 ,  G09G2300/0809 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2330/021 ,  G11C19/28 ,  H01L27/1225 ,  H01L29/1033 ,  H01L29/7869 ,  H03K19/00346

Abstract: To provide a novel shift register. Transistors 101 to 104 are provided. A first terminal of the transistor 101 is connected to a wiring 111 and a second terminal of the transistor 101 is connected to a wiring 112. A first terminal of the transistor 102 is connected to a wiring 113 and a second terminal of the transistor 102 is connected to the wiring 112. A first terminal of the transistor 103 is connected to the wiring 113 and a gate of the transistor 103 is connected to the wiring 111 or a wiring 119. A first terminal of the transistor 104 is connected to a second terminal of the transistor 103, a second terminal of the transistor 104 is connected to a gate of the transistor 101, and a gate of the transistor 104 is connected to a gate of the transistor 102.

Abstract translation: 提供一种新颖的移位寄存器。 提供晶体管101至104。 晶体管101的第一端子连接到布线111，晶体管101的第二端子连接到布线112.晶体管102的第一端子连接到布线113，晶体管102的第二端子 连接到布线112.晶体管103的第一端子连接到布线113，晶体管103的栅极连接到布线111或布线119.晶体管104的第一端子连接到第二端子 晶体管104的第二端子连接到晶体管101的栅极，并且晶体管104的栅极连接到晶体管102的栅极。

公开(公告)号：US09036767B2

公开(公告)日：2015-05-19

申请号：US14305367

申请日：2014-06-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G11C19/28 ,  G09G3/36 ,  G11C19/18

CPC classification number: G09G3/3677 ,  G09G3/3648 ,  G09G2300/0809 ,  G09G2310/0286 ,  G11C19/184 ,  G11C19/28 ,  H01L27/1225

Abstract: To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. When the transistor 13 or the transistor 14 is turned on in a non-selection period, the potential of a node A is set, so that the node A is prevented from entering into a floating state.

Abstract translation: 抑制移位寄存器电路的故障。 提供了具有多个触发器电路的移位寄存器。 触发器电路包括晶体管11，晶体管12，晶体管13，晶体管14和晶体管15.当晶体管13或晶体管14在非选择期间导通时，节点的电位 设置A，使得节点A被阻止进入浮动状态。

公开(公告)号：US20150077676A1

公开(公告)日：2015-03-19

申请号：US14554216

申请日：2014-11-26

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Atsushi Umezaki ,  Hiroyuki Miyake

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1368

CPC classification number: G02F1/1368 ,  G02F1/136286 ,  G09G3/20 ,  G09G3/2022 ,  G09G3/3233 ,  G09G3/3266 ,  G09G3/3275 ,  G09G3/342 ,  G09G3/3426 ,  G09G3/3677 ,  G09G3/3685 ,  G09G2300/043 ,  G09G2300/0852 ,  G09G2310/0248 ,  G09G2310/0262 ,  G09G2310/027 ,  G09G2310/0275 ,  G09G2310/0286 ,  G09G2310/0297 ,  G09G2320/0233 ,  G09G2320/043 ,  G09G2330/021 ,  G09G2340/02 ,  G09G2352/00 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/1255 ,  H01L27/156 ,  H01L27/3232 ,  H01L27/3276 ,  H01L29/42384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An object of the invention is to provide a circuit technique which enables reduction in power consumption and high definition of a display device. A switch controlled by a start signal is provided to a gate electrode of a transistor, which is connected to a gate electrode of a bootstrap transistor. When the start signal is input, a potential is supplied to the gate electrode of the transistor through the switch, and the transistor is turned off. The transistor is turned off, so that leakage of a charge from the gate electrode of the bootstrap transistor can be prevented. Accordingly, time for storing a charge in the gate electrode of the bootstrap transistor can be shortened, and high-speed operation can be performed.

Abstract translation: 本发明的目的是提供一种能够降低显示装置的功耗和高清晰度的电路技术。 将由启动信号控制的开关提供给晶体管的栅电极，该晶体管连接到自举晶体管的栅电极。 当输入起始信号时，通过开关将电位提供给晶体管的栅电极，晶体管截止。 晶体管截止，从而可以防止电荷从自举晶体管的栅电极泄漏。 因此，可以缩短在自举晶体管的栅电极中存储电荷的时间，并且可以执行高速操作。