公开(公告)号：US20170338349A1

公开(公告)日：2017-11-23

申请号：US15585849

申请日：2017-05-03

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Masashi TSUBUKU ,  Kazuaki OHSHIMA ,  Masashi FUJITA ,  Daigo SHIMADA ,  Tsutomu MURAKAWA

IPC: H01L29/786 ,  G11C11/401 ,  H01L27/12 ,  H01L27/1156

CPC classification number: H01L29/7869 ,  G11C11/401 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/78618 ,  H01L29/78621 ,  H01L29/78648 ,  H01L29/78696

Abstract: A semiconductor device that can measure a minute current. The semiconductor device includes a first transistor, a second transistor, a node, and a capacitor. The first transistor includes an oxide semiconductor in a channel formation region. The node is electrically connected to a gate of the second transistor and a first terminal of the capacitor. The node is brought into an electrically floating state by turning off the first transistor after a potential V0 is supplied. Change in a potential VFN of the node over time is expressed by Formula (1). In Formula (1), t is elapsed time after the node is brought into the electrically floating state, τ is a constant with a unit of time, and β is a constant greater than or equal to 0.4 and less than or equal to 0.6. V FN  ( t ) = V 0 × e - ( t τ ) β ( 1 )

公开(公告)号：US20170309754A1

公开(公告)日：2017-10-26

申请号：US15648943

申请日：2017-07-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Hiroki OHARA ,  Tatsuya HONDA ,  Takatsugu OMATA ,  Yusuke NONAKA ,  Masahiro TAKAHASHI ,  Akiharu MIYANAGA

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/04 ,  H01L29/10

CPC classification number: H01L29/78696 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/247 ,  H01L29/7869 ,  H01L29/78693

Abstract: An oxide semiconductor film which has more stable electric conductivity is provided. The oxide semiconductor film comprises a crystalline region. The oxide semiconductor film has a first peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.4 nm−1 and less than or equal to 0.7 nm−1 in a region where a magnitude of a scattering vector is greater than or equal to 3.3 nm−1 and less than or equal to 4.1 nm−1. The oxide semiconductor film has a second peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.45 nm−1 and less than or equal to 1.4 nm−1 in a region where a magnitude of a scattering vector is greater than or equal to 5.5 nm−1 and less than or equal to 7.1 nm−1.

公开(公告)号：US20170236949A1

公开(公告)日：2017-08-17

申请号：US15429234

申请日：2017-02-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kenichi OKAZAKI ,  Masashi TSUBUKU ,  Satoru SAITO ,  Noritaka ISHIHARA

IPC: H01L29/786 ,  H01L29/24 ,  H01L27/12 ,  H01L29/04

CPC classification number: H01L29/78696 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/24 ,  H01L29/78648 ,  H01L29/7869

Abstract: A semiconductor device with improved electrical characteristics is provided. A semiconductor device with improved field effect mobility is provided. A semiconductor device in which the field-effect mobility is not lowered even at high temperatures is provided. A semiconductor device which can be formed at low temperatures is provided. A semiconductor device with improved productivity can be provided. In the semiconductor device, there is a range of a gate voltage where the field-effect mobility increases as the temperature increases within a range of the gate voltage from 0 V to 10 V.For example, such a range of a gate voltage exists at temperatures ranging from a room temperature (25° C.) to 120° C. In the semiconductor device, the off-state current is kept extremely low (lower than or equal to the detection limit of a measurement device) within the above temperature range.

公开(公告)号：US20170186774A1

公开(公告)日：2017-06-29

申请号：US15460652

申请日：2017-03-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masayuki SAKAKURA ,  Yoshiaki OIKAWA ,  Shunpei YAMAZAKI ,  Junichiro SAKATA ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Miyuki HOSOBA

IPC: H01L27/12 ,  G02F1/1368 ,  G02F1/1343 ,  G02F1/1345

CPC classification number: H01L27/124 ,  G02F1/134309 ,  G02F1/13454 ,  G02F1/1368 ,  G02F2202/10 ,  H01L27/1225 ,  H01L27/1255

Abstract: The semiconductor device includes a driver circuit portion including a driver circuit and a pixel portion including a pixel. The pixel includes a gate electrode layer having a light-transimitting property, a gate insulating layer, a source electrode layer and a drain electrode layer each having a light-transmitting property provided over the gate insulating layer, an oxide semiconductor layer covering top surfaces and side surfaces of the source electrode layer and the drain electrode layer and provided over the gate electrode layer with the gate insulating layer therebetween, a conductive layer provided over part of the oxide semiconductor layer and having a lower resistance than the source electrode layer and the drain electrode layer, and an oxide insulating layer in contact with part of the oxide semiconductor layer.

公开(公告)号：US20170092776A1

公开(公告)日：2017-03-30

申请号：US15372493

申请日：2016-12-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Hiroyuki MIYAKE ,  Kei TAKAHASHI ,  Kouhei TOYOTAKA ,  Masashi TSUBUKU ,  Kosei NODA ,  Hideaki KUWABARA

IPC: H01L29/786 ,  H01L29/24 ,  G06K19/077 ,  H01L29/66 ,  H01L21/8236 ,  H01L23/66 ,  H01L27/088

CPC classification number: H01L29/26 ,  G06K19/07758 ,  G11C7/00 ,  G11C19/28 ,  H01L21/8236 ,  H01L23/66 ,  H01L27/0883 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78609 ,  H01L29/7869 ,  H01L29/78696 ,  H01L2223/6677 ,  H02M3/07

Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel fog nation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.

公开(公告)号：US20170040350A1

公开(公告)日：2017-02-09

申请号：US15332323

申请日：2016-10-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Masashi TSUBUKU ,  Kosei NODA

IPC: H01L27/12 ,  H03K17/16 ,  G09G3/20 ,  G11C19/28

CPC classification number: H01L27/1255 ,  G09G3/20 ,  G09G3/2092 ,  G09G3/3233 ,  G09G3/3291 ,  G09G3/36 ,  G09G3/3648 ,  G09G2300/0439 ,  G09G2300/08 ,  G09G2300/0842 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/184 ,  G11C19/28 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/7869 ,  H03K17/161 ,  H03K19/00315 ,  H03K19/096

Abstract: To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10−13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.

Abstract translation: 为了减小晶体管的漏电流，可以抑制逻辑电路的故障。 逻辑电路包括晶体管，其包括具有沟道形成层的功能的氧化物半导体层，并且其中截止电流在沟道宽度中为每微米1×10-13A或更小。 作为时钟信号的第一信号，第二信号和第三信号被输入作为输入信号。 作为输出信号输出第四信号和第五信号，其电压状态根据输入的第一至第三信号而被设定。

公开(公告)号：US20160300933A1

公开(公告)日：2016-10-13

申请号：US15190677

申请日：2016-06-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Hitoshi NAKAYAMA ,  Masashi TSUBUKU ,  Daigo SHIMADA

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/49 ,  H01L27/12 ,  H01L29/45

CPC classification number: H01L29/66969 ,  H01L22/14 ,  H01L27/088 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/7869

Abstract: When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. The side wall of the second film is slightly etched when a resist mask is removed after the second etching process.

Abstract translation: 当制造具有底栅底接触结构的晶体管时，例如，构成源极和漏极的导电层具有三层结构，并且执行两步蚀刻。 在第一蚀刻工艺中，采用其中至少第二膜和第三膜的蚀刻速率高的蚀刻方法，并且进行第一蚀刻处理直到至少第一膜暴露。 在第二蚀刻工艺中，第一膜的蚀刻速率高于第一蚀刻工艺中的蚀刻速率和“下面设置并与第一膜接触的”层的蚀刻速率的蚀刻方法低于 采用第一蚀刻工艺。 当在第二蚀刻工艺之后去除抗蚀剂掩模时，第二膜的侧壁被稍微蚀刻。

公开(公告)号：US20160190232A1

公开(公告)日：2016-06-30

申请号：US15063733

申请日：2016-03-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masahiro TAKAHASHI ,  Takuya HIROHASHI ,  Masashi TSUBUKU ,  Masashi OOTA

IPC: H01L29/04 ,  H01L29/26 ,  H01L29/786

CPC classification number: H01L29/04 ,  H01L29/045 ,  H01L29/24 ,  H01L29/247 ,  H01L29/26 ,  H01L29/7869 ,  H01L29/78693

Abstract: A highly reliable semiconductor device including an oxide semiconductor is provided. Provided is a semiconductor device including an oxide semiconductor layer, an insulating layer in contact with the oxide semiconductor layer, a gate electrode layer overlapping with the oxide semiconductor layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The oxide semiconductor layer includes a first region having a crystal whose size is less than or equal to 10 nm and a second region which overlaps with the insulating layer with the first region provided therebetween and which includes a crystal part whose c-axis is aligned in a direction parallel to a normal vector of the surface of the oxide semiconductor layer.

公开(公告)号：US20160155859A1

公开(公告)日：2016-06-02

申请号：US15017704

申请日：2016-02-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hajime KIMURA ,  Kengo AKIMOTO ,  Masashi TSUBUKU ,  Toshinari SASAKI

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L29/78693 ,  G09G3/3648 ,  G09G2300/0842 ,  H01L27/1225 ,  H01L29/78618

Abstract: A display device including a pixel having a memory. The pixel includes at least a display element, a capacitor, an inverter, and a switch. The switch is controlled with a signal held in the capacitor and a signal output from the inverter so that voltage is supplied to the display element. The inverter and the switch can be constituted by transistors with the same polarity. A semiconductor layer included in the pixel may be formed using a light-transmitting material. Moreover, a gate electrode, a drain electrode, and a capacitor electrode may be formed using a light-transmitting conductive layer. The pixel is formed using a light-transmitting material in such a manner, whereby the display device can be a transmissive display device while including a pixel having a memory.

Abstract translation: 一种显示装置，包括具有存储器的像素。 像素至少包括显示元件，电容器，反相器和开关。 开关由保持在电容器中的信号和从逆变器输出的信号控制，使得电压被提供给显示元件。 逆变器和开关可以由具有相同极性的晶体管构成。 可以使用透光材料形成包括在像素中的半导体层。 此外，可以使用透光导电层来形成栅电极，漏电极和电容器电极。 以这种方式使用透光材料形成像素，由此显示装置可以是包括具有存储器的像素的透射显示装置。

公开(公告)号：US20160064570A1

公开(公告)日：2016-03-03

申请号：US14936305

申请日：2015-11-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Masashi TSUBUKU ,  Kosei NODA

IPC: H01L29/786 ,  H01L27/12 ,  H01L27/02

CPC classification number: H01L29/7869 ,  H01L22/34 ,  H01L27/0207 ,  H01L27/1225 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×1019 (atoms/cm3) or less and thus substantially serves as an insulator in a state where an electric field is not generated. Therefore, off-state current of a thin film transistor can be reduced, leading to suppressing the leakage of electric charge stored in a capacitor, through the thin film transistor. Accordingly, a malfunction of the logic circuit can be prevented. Further, the excessive amount of current which flows in the logic circuit can be reduced through the reduction of off-state current of the thin film transistor, resulting in low power consumption of the logic circuit.

Abstract translation: 逻辑电路包括具有使用氧化物半导体形成的沟道形成区域的薄膜晶体管，以及通过关闭薄膜晶体管而使端子中的一个成为浮置状态的电容器。 氧化物半导体的氢浓度为5×1019（原子/ cm3）以下，因此在不产生电场的状态下基本上用作绝缘体。 因此，可以减小薄膜晶体管的截止电流，从而通过薄膜晶体管抑制存储在电容器中的电荷的泄漏。 因此，可以防止逻辑电路的故障。 此外，可以通过减小薄膜晶体管的截止电流来降低在逻辑电路中流动的过量的电流，导致逻辑电路的低功耗。