公开(公告)号：US06387797B1

公开(公告)日：2002-05-14

申请号：US09234292

申请日：1999-01-20

Applicant: Subhas Bothra ,  Rao Annapragada

Inventor： Subhas Bothra ,  Rao Annapragada

IPC: H01L214763

CPC classification number: H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing semiconductors is provided which avoids metal deposition in voids formed in the dielectric between interconnects. In a preferred embodiment, an etch stop recess portion is provided over the dielectric which encloses the interconnects to prevent via openings from extending into the voids during the etching of the via openings. Accordingly, metal deposition of the voids during metal deposition of the vias is avoided. As a result, the semiconductors so formed has reduced capacitance between the interconnects and improved reliability since the voids are cleared of any metal deposition.

Abstract translation: 提供一种制造半导体的方法，其避免了在互连之间的电介质中形成的空隙中的金属沉积。 在优选实施例中，蚀刻停止凹部部分设置在电介质上，封装互连件以防止在蚀刻通孔孔期间通孔开口延伸到空隙中。 因此，避免了在通孔的金属沉积期间空隙的金属沉积。 结果，如此形成的半导体具有减小互连之间的电容并提高可靠性，因为空隙被任何金属沉积清除。

公开(公告)号：US06277708B1

公开(公告)日：2001-08-21

申请号：US09396104

申请日：1999-09-14

Applicant: Subhas Bothra ,  Harlan Lee Sur, Jr.

Inventor： Subhas Bothra ,  Harlan Lee Sur, Jr.

IPC: H01L2176

CPC classification number: H01L21/28525 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/763 ,  H01L27/0814 ,  H01L29/861

Abstract: Disclosed is a semiconductor diode structure, and method for making semiconductor diode structures for suppressing transistor gate oxide plasma charging damage. The semiconductor diode structure includes a shallow trench isolation region that is configured to isolate an active region of a semiconductor substrate. A doped polysilicon electrode having a first end and a second end. The doped polysilicon electrode is defined in the shallow trench isolation region and the first end is configured to be in electrical contact with the semiconductor substrate. The diode structure further includes a polysilicon gate that has an underlying gate oxide. The polysilicon gate is defined over the active region and extends over part of the shallow trench isolation region so as to make electrical interconnection between the polysilicon gate and the second end of the doped polysilicon electrode.

Abstract translation: 公开了半导体二极管结构以及用于制造用于抑制晶体管栅极氧化物等离子体充电损坏的半导体二极管结构的方法。 半导体二极管结构包括被配置为隔离半导体衬底的有源区的浅沟槽隔离区。 一种具有第一端和第二端的掺杂多晶硅电极。 掺杂多晶硅电极限定在浅沟槽隔离区域中，并且第一端被配置为与半导体衬底电接触。 二极管结构还包括具有底层栅极氧化物的多晶硅栅极。 多晶硅栅极被限定在有源区上并且在浅沟槽隔离区的一部分上延伸，以便在多晶硅栅极和掺杂多晶硅电极的第二端之间形成电互连。

公开(公告)号：US06275971B1

公开(公告)日：2001-08-14

申请号：US08941898

申请日：1997-09-30

Applicant: Harold J. Levy ,  Subhas Bothra ,  David C. Chapman

Inventor： Harold J. Levy ,  Subhas Bothra ,  David C. Chapman

IPC: G06F1750

CPC classification number: G06F17/5081

Abstract: Disclosed is a method for checking integrated circuit layout design files. The method includes identifying a via geometry that is laid out on a via mask file. Identifying a metallization geometry that is laid out on a metallization mask file. Shifting the via geometry in a first orientation to produce a first shifted via geometry. Performing a logical AND between the first shifted via geometry and the metallization geometry. The method further includes determining whether the logical AND produces a value indicative of a sufficient overlap between the identified metallization geometry and the first shifted via geometry.

Abstract translation: 公开了一种用于检查集成电路布局设计文件的方法。 该方法包括识别布局在通孔掩模文件上的通孔几何。 识别在金属化掩模文件上布置的金属化几何。 在第一方向移动通孔几何以产生第一移位通孔几何形状。 在第一移位通孔几何和金属化几何之间执行逻辑AND。 该方法还包括确定逻辑“否”是否产生指示所识别的金属化几何形状和第一偏移通道几何之间的足够重叠的值。

公开(公告)号：US6159844A

公开(公告)日：2000-12-12

申请号：US87492

申请日：1998-05-29

Applicant: Subhas Bothra

Inventor： Subhas Bothra

IPC: H01L21/311 ,  H01L21/60 ,  H01L21/4763

CPC classification number: H01L21/76897 ,  H01L21/31116

Abstract: Disclosed is a method for fabricating conductive contacts in a dielectric layer that overlies a semiconductor wafer having diffusion regions, shallow trench isolation regions, and gate structures that have a part overlying the shallow trench isolation regions. The method includes forming an oxide layer over the gate structures and forming a photoresist mask over the semiconductor wafer, including the oxide layer over the gate structures. The photoresist mask has windows that define an opening over gate contact locations, and the gate contact locations are defined substantially over the part of the gate structures that overlie the shallow trench isolation regions. The method further includes etching the oxide layer over the gate structures through the windows to define exposed gate structure regions. The method also includes depositing a silicon nitride layer over the semiconductor wafer including the oxide layer over the gate structures and the exposed gate structure regions, and depositing a dielectric layer over the deposited silicon nitride layer. The method then includes etching via holes through the dielectric layer and the silicon nitride layer to define conductive contact vias to both the exposed gate structure regions and diffusion regions.

Abstract translation: 公开了一种在具有扩散区域的半导体晶片，浅沟槽隔离区域和具有覆盖浅沟槽隔离区域的部分的栅极结构的电介质层中制造导电接触的方法。 该方法包括在栅极结构上形成氧化物层，并在半导体晶片上形成光致抗蚀剂掩模，包括栅极结构上的氧化物层。 光致抗蚀剂掩模具有限定在栅极接触位置上的开口的窗口，并且栅极接触位置基本上限定在覆盖在浅沟槽隔离区域上的栅极结构的部分上。 该方法还包括通过窗口蚀刻栅极结构上的氧化物层以限定暴露的栅极结构区域。 该方法还包括在半导体晶片之上沉积包括栅极结构和暴露的栅极结构区域上的氧化物层的氮化硅层，以及在沉积的氮化硅层上沉积介电层。 该方法然后包括通过介电层和氮化硅层蚀刻通孔，以限定暴露的栅极结构区域和扩散区域的导电接触通孔。

公开(公告)号：US6140221A

公开(公告)日：2000-10-31

申请号：US124603

申请日：1998-07-29

Applicant: Rao Venkateswara Annapragada ,  Subhas Bothra

Inventor： Rao Venkateswara Annapragada ,  Subhas Bothra

IPC: H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/02134 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/3121 ,  H01L21/3124 ,  H01L21/31695 ,  H01L21/76802 ,  H01L21/76831

Abstract: A semiconductor device has a device layer, a conductive structure, such as a conductive line, disposed over the device layer, and a porous dielectric layer disposed over the device layer and the conductive structure. At least one via is formed through the porous dielectric layer to the conductive structure with a second dielectric material formed along sidewalls of the via. Often, the porous dielectric layer includes a hydrophobic aerogel material having silicon-hydrogen bonds. One exemplary method of making the semiconductor device includes forming a conductive structure over a device layer of the semiconductor device and then forming a porous dielectric layer over the device layer and the conductive structure. A first via is formed through the porous dielectric layer to the conductive structure. The first via is filled with a second dielectric material that is less porous than the porous dielectric layer and then a second via is formed through the second dielectric material to the conductive structure.

Abstract translation: 半导体器件具有设置在器件层上的器件层，导电结构，例如导线，以及设置在器件层和导电结构上的多孔介电层。 至少一个通孔通过多孔电介质层形成到导电结构，其中第二电介质材料沿通孔的侧壁形成。 通常，多孔介电层包括具有硅 - 氢键的疏水性气凝胶材料。 制造半导体器件的一个示例性方法包括在半导体器件的器件层上形成导电结构，然后在器件层和导电结构上形成多孔介电层。 通过多孔介电层形成第一通孔到导电结构。 第一通孔填充有比多孔电介质层少孔的第二电介质材料，然后通过第二电介质材料形成导电结构的第二通孔。

公开(公告)号：US6140188A

公开(公告)日：2000-10-31

申请号：US83251

申请日：1998-05-20

Applicant: Harlan Sur ,  Subhas Bothra

Inventor： Harlan Sur ,  Subhas Bothra

IPC: H01L27/06 ,  H01L27/11 ,  H01L21/336

CPC classification number: H01L27/0676 ,  H01L27/11

Abstract: A small-area, high-resistance load device is fabricated in the same area used for the shallow trench isolation region. In an example embodiment, the load device comprises a series resistor coupled to a poly-silicon diode. In one example application, the load device acts as a pull-up device replacing standard PMOS pull-up loads used in connection with static memory cells, thereby increasing the cell density of a static memory array.

Abstract translation: 在用于浅沟槽隔离区域的相同区域中制造小面积，高电阻负载装置。 在示例性实施例中，负载装置包括耦合到多晶硅二极管的串联电阻器。 在一个示例应用中，负载设备用作上拉设备，替代与静态存储器单元相关联使用的标准PMOS上拉负载，从而增加静态存储器阵列的单元密度。

公开(公告)号：US6133111A

公开(公告)日：2000-10-17

申请号：US164167

申请日：1998-09-30

Applicant: Harlan Sur ,  Subhas Bothra

Inventor： Harlan Sur ,  Subhas Bothra

IPC: G03F9/00 ,  H01L23/544 ,  H01L21/76

CPC classification number: G03F9/708 ,  G03F9/70 ,  G03F9/7084 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002

Abstract: A photo alignment structure integral with a substrate enables the alignment apparatus to receive a reflected light signature of the surface topography of the alignment structure. As the circuit is constructed, the alignment target may be built in tandem with the process. The alignment structure is constructed so that its surface will retain sufficient topography to enable the alignment apparatus to properly align.

Abstract translation: 与基板一体的光取向结构使得对准装置能够接收对准结构的表面形貌的反射光标记。 当构建电路时，可以与该过程一起构建对准目标。 对准结构被构造成使得其表面将保持足够的形貌以使对准装置能够正确对准。

公开(公告)号：US6057224A

公开(公告)日：2000-05-02

申请号：US899531

申请日：1997-07-24

Applicant: Subhas Bothra ,  Ling Q. Qian

Inventor： Subhas Bothra ,  Ling Q. Qian

IPC: H01L21/768 ,  H01L23/482 ,  H01L23/522 ,  H01L21/44 ,  H01L21/461

CPC classification number: H01L21/7682 ,  H01L23/4821 ,  H01L23/5221 ,  H01L2924/0002 ,  Y10S438/926

Abstract: A method of making an integrated circuit interconnect structure having air as the effective dielectric between metallization layers includes the steps of: a) providing an air dielectric formation layer of a sacrificial material over a substrate; b) forming a pillar holes in the air dielectric formation layer; c) filling the pillar holes with a non-sacrificial material; d) constructing a metallization layer over the sacrificial air dielectric formation layer and non-sacrificial material pillars; and e) applying an isotropic etchant to the interconnect structure to remove the sacrificial material, leaving the non-sacrificial material pillars for mechanical support of the metallization layer. An interconnect structure having an air dielectric includes a bottom metallization layer, a top metallization layer, and a plurality of pillars separating the bottom and top metallization layers and mechanically supporting the top metallization layer. Additional similar interconnect structures can be stacked over a base interconnect structure.

Abstract translation: 制造具有空气作为金属化层之间的有效电介质的集成电路互连结构的方法包括以下步骤：a）在衬底上提供牺牲材料的空气电介质形成层; b）在空气电介质形成层中形成柱孔; c）用非牺牲材料填充柱孔; d）在牺牲空气电介质形成层和非牺牲材料柱之上构建金属化层; 以及e）向互连结构施加各向同性蚀刻剂以除去牺牲材料，留下用于金属化层的机械支撑的非牺牲材料柱。 具有空气电介质的互连结构包括底部金属化层，顶部金属化层和分离底部和顶部金属化层并机械地支撑顶部金属化层的多个柱。 附加的类似互连结构可以堆叠在基底互连结构上。

公开(公告)号：US6054378A

公开(公告)日：2000-04-25

申请号：US104753

申请日：1998-06-25

Applicant: Stephen L. Skala ,  Subhas Bothra

Inventor： Stephen L. Skala ,  Subhas Bothra

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763

CPC classification number: H01L21/76843 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002

Abstract: Disclosed is a method for encapsulating a via over a first metal layer of a semiconductor substrate in a damascene processing to prevent voiding. The method includes forming an intermetal oxide (IMO) layer over the first metal layer and forming a via in the IMO layer such that the via exposes a portion of the first metal layer and a side wall of the via in the IMO layer. The method also includes conformally forming a first barrier layer over the IMO layer and the via such that a portion of the first barrier layer is deposited over the side wall of the IMO layer and the exposed portion of the first metal layer. The method further includes depositing a second metal layer over the first barrier layer such that the second metal layer fills the via within the first barrier layer portion deposited in the via to form a metal via. Additionally, the method includes removing the second metal layer and the first barrier layer above a top portion of the IMO layer and forming a trench in a portion of the IMO layer in contact with the first barrier layer to a specified depth. The method further includes forming a second barrier layer in the trench. The method also forming a third metal layer over the second barrier layer in the trench to form a metal trench such that the metal via is encapsulated by the first barrier layer so as to reduce electromigration effect in the metal via.

Abstract translation: 公开了一种用于在大马士革处理中在半导体衬底的第一金属层上封装通孔以防止空隙的方法。 该方法包括在第一金属层上形成金属间氧化物（IMO）层，并在IMO层中形成通孔，使得通孔在IMO层中露出第一金属层的一部分和通孔的侧壁。 该方法还包括在IMO层和通孔上保形地形成第一阻挡层，使得第一阻挡层的一部分沉积在IMO层的侧壁和第一金属层的暴露部分上。 该方法还包括在第一阻挡层上沉积第二金属层，使得第二金属层填充沉积在通孔中的第一势垒层部分内的通孔以形成金属通孔。 此外，该方法包括在IMO层的顶部上方去除第二金属层和第一阻挡层，并在与第一阻挡层接触的IMO层的一部分中形成沟槽至特定深度。 该方法还包括在沟槽中形成第二阻挡层。 该方法还在沟槽中的第二阻挡层上形成第三金属层以形成金属沟槽，使得金属通孔被第一阻挡层封装，以便降低金属通孔中的电迁移效应。

公开(公告)号：US6046102A

公开(公告)日：2000-04-04

申请号：US196481

申请日：1998-11-19

Applicant: Subhas Bothra ,  Ling Q. Qian

Inventor： Subhas Bothra ,  Ling Q. Qian

IPC: H01L23/00 ,  H01L23/29 ,  H01L21/4763 ,  H01L21/31

CPC classification number: H01L23/564 ,  H01L23/291 ,  H01L2924/0002

Abstract: Disclosed is a method for making a passivation coated semiconductor structure. The method includes providing a substrate having a metallization line patterned over the substrate. The metallization line defining at least one interconnect feature having a first thickness, and depositing a first silicon nitride barrier layer having a second thickness over the substrate and the metallization line. The method further including applying an oxide material over the first silicon nitride barrier layer that overlies the substrate and the metallization line. The oxide application includes a deposition component and a sputtering component, and the sputtering component is configured to remove at least a part of an edge of the first silicon nitride layer. The edge is defined by the metallization line underlying the first silicon nitride layer. Further, the method includes depositing a second silicon nitride layer over the oxide material that is applied by the deposition component and the edge of the first silicon nitride layer sputtered by the sputtering component to establish a moisture and mobile ion repelling barrier between the second and first silicon nitride layers.

Abstract translation: 公开了一种制备钝化涂层半导体结构的方法。 该方法包括提供具有在衬底上图案化的金属化线的衬底。 金属化线限定具有第一厚度的至少一个互连特征，以及在衬底和金属化线上沉积具有第二厚度的第一氮化硅阻挡层。 所述方法还包括在覆盖在衬底和金属化线上的第一氮化硅阻挡层上施加氧化物材料。 氧化物应用包括沉积部件和溅射部件，并且溅射部件被配置为去除第一氮化硅层的边缘的至少一部分。 边缘由第一氮化硅层下面的金属化线限定。 此外，该方法包括在由沉积部件施加的氧化物材料上沉积第二氮化硅层和由溅射部件溅射的第一氮化硅层的边缘，以在第二和第一之间建立湿气和可移动的离子排斥势垒 氮化硅层。