公开(公告)号：US10892209B2

公开(公告)日：2021-01-12

申请号：US16363468

申请日：2019-03-25

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Nazila Dadvand ,  Sreenivasan Koduri

IPC: H01L23/495 ,  H01L21/48

Abstract: A semiconductor device includes a metal substrate including a through-hole aperture having a multi-size cavity including a larger area first cavity portion above a smaller area second cavity portion that defines a first ring around the second cavity portion, where the first cavity portion is sized with area dimensions to receive a semiconductor die having a top side with circuitry coupled to bond pads thereon and a back side with a metal (BSM) layer thereon. The semiconductor die is mounted top side up with the BSM layer on the first ring. A metal die attach layer directly contacts the BSM layer, sidewalls of the bottom cavity portion, and a bottom side of the metal substrate.

公开(公告)号：US10832993B1

公开(公告)日：2020-11-10

申请号：US16408108

申请日：2019-05-09

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Sreenivasan Koduri ,  Benjamin Stassen Cook

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A leadless multichip semiconductor device includes a metal substrate having a through-hole aperture with an outer ring for holding a bottom semiconductor die with an inner row and an outer row of metal pads. The bottom semiconductor die has a back side metal (BSM) layer on its bottom side and a top side with bond pads mounted top side up on the ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate providing a die attachment that fills a bottom portion of the aperture. Bond wires are between the inner metal pads and the bond pads. A top semiconductor die has top bond pads mounted top side up on a dielectric adhesive on the bottom semiconductor die. Pins connect the top bond pads to the outer metal pads. A mold compound provides isolation between adjacent ones of the metal pads.

公开(公告)号：US10796956B2

公开(公告)日：2020-10-06

申请号：US16022956

申请日：2018-06-29

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/532

Abstract: Described examples provide microelectronic devices and fabrication methods, including fabricating a contact structure by forming a titanium or titanium tungsten barrier layer on a conductive feature, forming a tin seed layer on the barrier layer, forming a copper structure on the seed layer above the conductive feature of the wafer or die, heating the seed layer and the copper structure to form a bronze material between the barrier layer and the copper structure, removing the seed layer using an etching process that selectively removes an exposed portion of the seed layer, and removing an exposed portion of the barrier layer.

公开(公告)号：US10692830B2

公开(公告)日：2020-06-23

申请号：US16038598

申请日：2018-07-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L23/00

Abstract: A structure for a semiconductor device includes a copper (Cu) layer and a first nickel (Ni) alloy layer with a Ni grain size a1. The structure also includes a second Ni alloy layer with a Ni grain size a2, wherein a1

公开(公告)号：US10607931B2

公开(公告)日：2020-03-31

申请号：US16026371

申请日：2018-07-03

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Christopher Daniel Manack

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/532

Abstract: A packaged semiconductor device includes a metal substrate having a center aperture with a plurality of raised traces around the center aperture including a metal layer on a dielectric base layer. A semiconductor die that has a back side metal (BSM) layer is mounted top side up in a top portion of the center aperture. A single metal layer directly between the BSM layer and walls of the metal substrate bounding the center aperture to provide a die attachment that fills a bottom portion of the center aperture. Leads having at least one bend that contact the metal layer are on the plurality of traces and include a distal portion that extends beyond the metal substrate. Bond wires are between the traces and bond pads on the semiconductor die. A mold compound provides encapsulation.

公开(公告)号：US20190109062A1

公开(公告)日：2019-04-11

申请号：US15909679

申请日：2018-03-01

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Keith Edward Johnson ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: A method for fabricating a copper pillar. The method includes forming a layer of titanium tungsten (TiW) over a semiconductor wafer, forming a layer of zinc (Zn) over the layer of TiW, and forming a copper pillar over the via. In addition, the method includes performing an anneal to diffuse the layer of Zn into the copper pillar. A semiconductor device that includes a layer of TiW coupled to a via of a semiconductor wafer and a copper pillar coupled to the layer of TiW. The copper pillar has interdiffused Zn within its bottom portion. Another method for fabricating a copper pillar includes forming a layer of TiW over a semiconductor wafer, forming a first patterned photoresist, forming a layer of Zn, and then removing the first patterned photoresist. The method further includes forming a second patterned photoresist and forming a copper pillar.

公开(公告)号：US20190088608A1

公开(公告)日：2019-03-21

申请号：US15954254

申请日：2018-04-16

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Salvatore Frank Pavone ,  Christopher Daniel Manack

IPC: H01L23/00 ,  C25D5/12

CPC classification number: H01L24/11 ,  C25D3/30 ,  C25D3/38 ,  C25D3/56 ,  C25D3/562 ,  C25D3/60 ,  C25D5/022 ,  C25D5/10 ,  C25D5/12 ,  C25D5/18 ,  C25D5/505 ,  C25D7/00 ,  C25D7/123 ,  H01L21/288 ,  H01L23/49524 ,  H01L23/49582 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05096 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13284 ,  H01L2224/13582 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13639 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/1368 ,  H01L2224/13684 ,  H01L2224/13693 ,  H01L2224/16245 ,  H01L2224/16503 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01042 ,  H01L2924/01027 ,  H01L2924/01028

Abstract: A microelectronic device includes a reflow structure. The reflow structure has a copper-containing member and a solder member, and a barrier layer between them. The barrier layer has metal grains, with a diffusion barrier filler between the metal grains. The metal grains include at least a first metal and a second metal, each selected from nickel, cobalt, lanthanum, and cerium, with each having a concentration in the metal grains of at least 10 weight percent. The diffusion barrier filler includes at least a third metal, selected from tungsten and molybdenum. A combined concentration of tungsten and molybdenum in the diffusion barrier filler is higher than in the metal grains to provide a desired resistance to diffusion of copper. The barrier layer includes 2 weight percent to 15 weight percent of the combined concentration of tungsten, and molybdenum. A bump bond structure and a lead frame package are disclosed.

公开(公告)号：US20250046621A1

公开(公告)日：2025-02-06

申请号：US18362635

申请日：2023-07-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand ,  Xuan Mo Li ,  Huo Yun Duan

IPC: H01L21/48 ,  H01L21/683 ,  H01L23/495

Abstract: A method for forming integrated circuit (IC) packages includes mounting tape on a mold compound of a strip of flat no-leads IC packages. The method also includes sawing the mold compound of the strip of flat no-leads IC packages to form singulated IC packages mounted on the tape. The method further includes immersing the singulated IC packages in a bath of immersion tin to form immersion tin plating on a flank of leads of the singulated IC packages.

公开(公告)号：US12139569B2

公开(公告)日：2024-11-12

申请号：US17675055

申请日：2022-02-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand ,  Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo

IPC: C08F292/00 ,  C08F8/42 ,  C08J5/00 ,  C08K3/04 ,  C08K3/08 ,  C08K7/00 ,  C08L25/06 ,  C08L33/12 ,  G03F1/78

Abstract: A method of forming a composite material includes photo-initiating a polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice. Unpolymerized monomer is removed from the polymer microlattice. The polymer microlattice is coated with a metal. The metal-coated polymer microlattice is dispersed in a polymer matrix.

公开(公告)号：US20240363504A1

公开(公告)日：2024-10-31

申请号：US18308956

申请日：2023-04-28

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49582 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49575 ,  H01L24/48 ,  H01L2224/48247

Abstract: An electronic device includes a semiconductor die, a package structure enclosing the semiconductor die, and a conductive lead having first and second surfaces. The first surface has a bilayer exposed along a side of the package structure, and the second surface is exposed along another side of the package structure. The bilayer includes first and second plated layers, the first plated layer on and contacting the first surface of the conductive lead and the second plated layer on and contacting the first plated layer and exposed along the side of the package structure, where the first plated layer includes nickel tungsten, and the second plated layer includes tin.