公开(公告)号：US10147752B2

公开(公告)日：2018-12-04

申请号：US15710419

申请日：2017-09-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Shyh-Fann Ting ,  Wei Chuang Wu ,  Yen-Ting Chiang ,  Kuan-Tsun Chen

IPC: H01L27/146

Abstract: In some embodiments, the present disclosure relates to a method of forming a back-side image (BSI) sensor. The method may be performed by forming an image sensing element within a substrate and forming a pixel-level memory node at a position within the substrate that is laterally offset from the image sensing element. A back-side of the substrate is etched to form one or more trenches that are laterally separated from the image sensing element by the substrate and that vertically overlie the pixel-level memory node. A reflective material is formed within the one or more trenches.

公开(公告)号：US10062720B2

公开(公告)日：2018-08-28

申请号：US15635673

申请日：2017-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chiang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsiao-Hui Tseng ,  Chih-Hui Huang ,  Shyh-Fann Ting ,  Shih Pei Chou ,  Sheng-Chan Li

IPC: H01L29/76 ,  H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14689

Abstract: The present disclosure relates to an integrated circuit, and an associated method of formation. In some embodiments, the integrated circuit comprises a deep trench grid disposed at a back side of a substrate. A passivation layer lines the deep trench grid within the substrate. The passivation layer includes a first high-k dielectric layer and a second high-k dielectric layer disposed over the first high-k dielectric layer. A first dielectric layer is disposed over the passivation layer, lining the deep trench grid and extending over an upper surface of the substrate. A second dielectric layer is disposed over the first dielectric layer and enclosing remaining spaces of the deep trench grid to form air-gaps at lower portions of the deep trench grid. The air-gaps are sealed by the first dielectric layer or the second dielectric layer below the upper surface of the substrate.

公开(公告)号：US10038026B2

公开(公告)日：2018-07-31

申请号：US15088232

申请日：2016-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sin-Yao Huang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Ming-Tsong Wang ,  Shih Pei Chou

IPC: H01L27/146

CPC classification number: H01L27/1464 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/1469

Abstract: Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3DIC includes a first substrate including a photodetector which is configured to receive light in a first direction from a light source. An interconnect structure is disposed over the first substrate, and includes a plurality of metal layers and insulating layers that are over stacked over one another in alternating fashion. One of the plurality of metal layers is closest to the light source and another of the plurality of metal layers is furthest from the light source. A bond pad recess extends into the interconnect structure from an opening in a surface of the 3DIC which is nearest the light source and terminates at a bond pad. The bond pad is spaced apart from the surface of the 3DIC and is in direct contact with the one of the plurality of metal layers that is furthest from the light source.

公开(公告)号：US20180151522A1

公开(公告)日：2018-05-31

申请号：US15880684

申请日：2018-01-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hsien Yang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Sin-Yao Huang

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L27/146 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L24/05 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/43 ,  H01L24/46 ,  H01L24/48 ,  H01L24/73 ,  H01L24/80 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L27/14634 ,  H01L2224/02126 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05096 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2224/73251 ,  H01L2224/73265 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2224/45099 ,  H01L2224/80001 ,  H01L2224/08 ,  H01L2224/48 ,  H01L2224/32 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/13 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/82 ,  H01L2924/01029 ,  H01L2924/00

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a first surface, a second surface opposing the first surface, and sidewalls defining a recess that passes through the semiconductor substrate. A first interconnect layer is within a first dielectric structure disposed along the second surface, and a bonding pad is in the recess and extends to the first interconnect layer. A dielectric filling layer is also within the recess. The dielectric filling layer has an opening over a portion of the bonding pad and a curved upper surface over the bonding pad. A nickel layer is over the bonding pad and in the opening.

公开(公告)号：US09978791B2

公开(公告)日：2018-05-22

申请号：US14815366

申请日：2015-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Tse-Hua Lu ,  Ching-Chun Wang ,  Jhy-Jyi Sze ,  Ping-Fang Hung

IPC: H01L27/146

CPC classification number: H01L27/14621 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/1469

Abstract: An image sensor structure and a method for forming the same are provided. The image sensor structure includes a first substrate including a first radiation sensing region and a first interconnect structure formed over a front side of the first substrate. The image sensor structure further includes a second substrate including a second radiation sensing region and a second interconnect structure formed over a front side of the second substrate. In addition, the first interconnect structure is bonded with the second interconnect structure.

公开(公告)号：US09881884B2

公开(公告)日：2018-01-30

申请号：US14933619

申请日：2015-11-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Hsien Yang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Sin-Yao Huang

IPC: H01L23/52 ,  H01L23/532 ,  H01L23/00 ,  H01L23/522 ,  H01L23/48 ,  H01L21/768 ,  H01L27/146

CPC classification number: H01L24/05 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/43 ,  H01L24/46 ,  H01L24/48 ,  H01L24/73 ,  H01L24/80 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L27/14634 ,  H01L2224/02126 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05096 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48229 ,  H01L2224/73251 ,  H01L2224/73265 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2224/45099 ,  H01L2224/80001 ,  H01L2224/08 ,  H01L2224/48 ,  H01L2224/32 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/13 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/82 ,  H01L2924/01029

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor substrate having a first surface, a second surface, and a recess. The second surface is opposite to the first surface. The recess passes through the first semiconductor substrate. The semiconductor device structure includes a first wiring layer over the second surface. The semiconductor device structure includes a first bonding pad in the recess and extending to the first wiring layer so as to be electrically connected to the first wiring layer. The semiconductor device structure includes a nickel layer over the first bonding pad. The semiconductor device structure includes a gold layer over the nickel layer.

公开(公告)号：US09871070B2

公开(公告)日：2018-01-16

申请号：US15016502

申请日：2016-02-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Hsuan Hsu ,  Ching-Chun Wang ,  Chien-Hsien Tseng ,  Chen-Jong Wang ,  Feng-Chi Hung ,  Wen-I Hsu

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14645 ,  H01L27/14647 ,  H01L27/14678 ,  H01L27/14685 ,  H01L27/14687

Abstract: A backside illuminated (BSI) image sensor for biased backside deep trench isolation (BDTI) and/or biased backside shielding is provided. A photodetector is arranged in a semiconductor substrate, laterally adjacent to a peripheral opening in the semiconductor substrate. An interconnect structure is arranged under the semiconductor substrate. A pad structure is arranged in the peripheral opening, and protrudes through a lower surface of the peripheral opening to the interconnect structure. A conductive layer is electrically coupled to the pad structure, and extends laterally towards the photodetector from over the pad structure. A method for manufacturing the BSI image sensor is also provided.

公开(公告)号：US09812483B2

公开(公告)日：2017-11-07

申请号：US15149497

申请日：2016-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Shyh-Fann Ting ,  Wei Chuang Wu ,  Yen-Ting Chiang ,  Kuan-Tsun Chen

IPC: H01L27/148 ,  H01L27/146

CPC classification number: H01L27/14629 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/14689

Abstract: In some embodiments, the present disclosure relates to a back-side image (BSI) sensor having a global shutter pixel with a reflective material that prevents contamination of a pixel-level memory node. In some embodiments, the BSI image sensor has an image sensing element arranged within a semiconductor substrate and a pixel-level memory node arranged within the semiconductor substrate at a location laterally offset from the image sensing element. A reflective material is also arranged within the semiconductor substrate at a location between the pixel-level memory node and a back-side of the semiconductor substrate. The reflective material has an aperture that overlies the image sensing element. The reflective material allows incident radiation to reach the image sensing element while preventing the incident radiation from reaching the pixel-level memory node, thereby preventing contamination of the pixel-level memory node.

公开(公告)号：US20170287878A1

公开(公告)日：2017-10-05

申请号：US15626834

申请日：2017-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sin-Yao Huang ,  Chun-Chieh Chuang ,  Ching-Chun Wang ,  Sheng-Chau Chen ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Yung-Lung Lin

IPC: H01L25/065 ,  H01L25/00 ,  H01L27/146 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/49838 ,  H01L23/52 ,  H01L25/50 ,  H01L27/14634 ,  H01L27/14636 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: In some embodiments, the present disclosure relates to a multi-dimensional integrated chip having a redistribution structure vertically extending between integrated chip die at a location laterally offset from a bond pad. The integrated chip structure has a first die and a second die. The first die has a first plurality of interconnect layers arranged within a first dielectric structure disposed on a first substrate. The second die has a second plurality of interconnect layers arranged within a second dielectric structure disposed between the first dielectric structure and a second substrate. A bond pad is disposed within a recess extending through the second substrate. A redistribution structure electrically couples the first die to the second die at a position that is laterally offset from the bond pad.

公开(公告)号：US20170186802A1

公开(公告)日：2017-06-29

申请号：US15380186

申请日：2016-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sin-Yao Huang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung

IPC: H01L27/146 ,  H01L31/02

CPC classification number: H01L27/14636 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/14689

Abstract: Some embodiments of the present disclosure relate to an integrated chip having a via support structure underlying a bond pad. The integrated chip has an image sensing element arranged within a substrate. A bond pad region extends through the substrate, at a location laterally offset from the image sensing element, to a first metal interconnect wire arranged within a dielectric structure along a front-side of the substrate. A bond pad is arranged within the bond pad region and contacts the first metal interconnect wire. A via support structure is arranged within the dielectric structure and has one or more vias that are separated from the bond pad by the first metal interconnect wire. One or more additional vias are arranged within the dielectric structure at a location laterally offset from the bond pad region. The one or more vias have larger sizes than the one or more additional vias.