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41.
公开(公告)号:US20210082830A1
公开(公告)日:2021-03-18
申请号:US16572609
申请日:2019-09-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Yu-Ming Lee , Chiang-Hao Lee , Hung-Jui Kuo , Ming-Che Ho
IPC: H01L23/532 , H01L23/00 , H01L21/768 , H01L21/56 , H01L23/528 , H01L23/31 , H01L21/02 , H01L23/522
Abstract: A package structure includes a semiconductor die and a redistribution circuit structure. The redistribution circuit structure is disposed on and electrically connected to the semiconductor die and includes a metallization layer and a dielectric layer disposed on the metallization layer. The metallization layer has conductive patterns, where each of the conductive patterns includes crystal grains, the crystal grains each are in a column shape and include a plurality of first banded structures having copper atoms oriented on a (220) lattice plane.
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公开(公告)号:US20190267314A1
公开(公告)日:2019-08-29
申请号:US15905756
申请日:2018-02-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Tzung-Hui Lee , Hung-Jui Kuo , Ming-Che Ho
IPC: H01L23/498 , H01L23/31 , H01L21/48 , H01L25/11
Abstract: A package structure, a RDL structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a RDL structure, and a connector. The encapsulant is aside the die. The RDL structure is electrically connected to the die. The connector is connected to the die through the RDL structure. The RDL structure includes a dielectric layer, a first RDL and a second RDL. The dielectric layer is on the encapsulant and the die. The first RDL is penetrating through the dielectric layer to connect to the die, the first RDL comprises a first via and a first trace on the first via. The second RDL is on the first RDL. The second RDL comprises a second via and a second trace on the second via. The second via contacts and covers a portion of a top surface and a portion of sidewalls of the first trace.
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公开(公告)号:US20190148255A1
公开(公告)日:2019-05-16
申请号:US15884397
申请日:2018-01-31
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shih-Hao Tseng , Hung-Jui Kuo , Ming-Che Ho , Chia-Hung Liu
IPC: H01L23/31 , H01L23/498 , H01L21/48 , H01L21/56 , H01L23/00
CPC classification number: H01L23/3128 , H01L21/4853 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/49811 , H01L23/49827 , H01L24/11 , H01L24/14 , H01L24/17 , H01L24/19 , H01L24/20 , H01L24/81 , H01L24/97 , H01L25/105 , H01L25/50 , H01L2221/68345 , H01L2221/68359 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/16227 , H01L2224/214 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/73267 , H01L2224/92125 , H01L2224/92244 , H01L2224/97 , H01L2225/0651 , H01L2225/06568 , H01L2225/1035 , H01L2225/1058 , H01L2924/15311 , H01L2924/18162 , H01L2924/19011 , H01L2924/00014 , H01L2924/00012 , H01L2924/013 , H01L2224/83
Abstract: A semiconductor package includes an encapsulated semiconductor device, a redistribution structure, and a protection layer. The encapsulated semiconductor device includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. The redistribution structure is disposed on the encapsulated semiconductor device and includes a dielectric layer and a redistribution circuit layer electrically connected to the semiconductor device. The protection layer at least covers the dielectric layer, wherein an oxygen permeability or a water vapor permeability of the protection layer is substantially lower than an oxygen permeability or a vapor permeability of the dielectric layer.
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公开(公告)号:US10074623B2
公开(公告)日:2018-09-11
申请号:US15880568
申请日:2018-01-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Tzung-Hui Lee , Hung-Jui Kuo , Ming-Che Ho , Tzu-Yun Huang
IPC: H01L23/00
CPC classification number: H01L24/02 , H01L21/568 , H01L21/6835 , H01L23/544 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/19 , H01L24/20 , H01L2221/68318 , H01L2221/68359 , H01L2221/68381 , H01L2223/54426 , H01L2223/54453 , H01L2224/02315 , H01L2224/02331 , H01L2224/02373 , H01L2224/02379 , H01L2224/0401 , H01L2224/05024 , H01L2224/11015 , H01L2224/12105 , H01L2224/13026 , H01L2224/131 , H01L2224/14181 , H01L2224/16225 , H01L2224/16265 , H01L2924/014
Abstract: A redistribution circuit structure electrically connected to at least one conductor underneath is provided. The redistribution circuit structure includes a dielectric layer, an alignment, and a redistribution conductive layer. The dielectric layer covers the conductor and includes at least one contact opening for exposing the conductor. The alignment mark is disposed on the dielectric layer. The alignment mark includes a base portion on the dielectric layer and a protruding portion on the base portion, wherein a ratio of a maximum thickness of the protruding portion to a thickness of the base portion is smaller than 25%. The redistribution conductive layer is disposed on the dielectric layer. The redistribution conductive layer includes a conductive via, and the conductive via is electrically connected to the conductor through the contact opening. A method of fabricating the redistribution circuit structure and an integrated fan-out package are also provided.
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45.
公开(公告)号:US20170271283A1
公开(公告)日:2017-09-21
申请号:US15164888
申请日:2016-05-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Tzung-Hui Lee , Hung-Jui Kuo , Ming-Che Ho , Tzu-Yun Huang
IPC: H01L23/00
CPC classification number: H01L24/02 , H01L21/568 , H01L21/6835 , H01L23/544 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/19 , H01L24/20 , H01L2221/68318 , H01L2221/68359 , H01L2221/68381 , H01L2223/54426 , H01L2223/54453 , H01L2224/02315 , H01L2224/02331 , H01L2224/02373 , H01L2224/02379 , H01L2224/0401 , H01L2224/05024 , H01L2224/11015 , H01L2224/12105 , H01L2224/13026 , H01L2224/131 , H01L2224/14181 , H01L2224/16225 , H01L2224/16265 , H01L2924/014
Abstract: A redistribution circuit structure electrically connected to at least one conductor underneath is provided. The redistribution circuit structure includes a dielectric layer, an alignment, and a redistribution conductive layer. The dielectric layer covers the conductor and includes at least one contact opening for exposing the conductor. The alignment mark is disposed on the dielectric layer. The alignment mark includes a base portion on the dielectric layer and a protruding portion on the base portion, wherein a ratio of a maximum thickness of the protruding portion to a thickness of the base portion is smaller than 25%. The redistribution conductive layer is disposed on the dielectric layer. The redistribution conductive layer includes a conductive via, and the conductive via is electrically connected to the conductor through the contact opening. A method of fabricating the redistribution circuit structure and an integrated fan-out package are also provided.
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