公开(公告)号：US20240297074A1

公开(公告)日：2024-09-05

申请号：US18661874

申请日：2024-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Shih Wang ,  Chun-I Tsai ,  Shian Wei Mao ,  Ken-Yu Chang ,  Ming-Hsing Tsai ,  Wei-Jung Lin

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/485 ,  H01L23/532

CPC classification number: H01L21/76847 ,  H01L21/32134 ,  H01L21/76846 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.

公开(公告)号：US11973117B2

公开(公告)日：2024-04-30

申请号：US17392320

申请日：2021-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsien Huang ,  Chang-Ting Chung ,  Wei-Cheng Lin ,  Wei-Jung Lin ,  Chih-Wei Chang

IPC: H01L29/40 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L21/768 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/321

CPC classification number: H01L29/401 ,  H01L21/02063 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/28568 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76879 ,  H01L29/41791 ,  H01L29/66795 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/3065 ,  H01L21/3212 ,  H01L21/7684 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7848

Abstract: Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein. Methods include etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact and repairing silicon oxide structures along sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer to prevent selective loss defects from occurring during a subsequent selective deposition of conductive fill materials and during subsequent etching of other contact openings. The methods further include performing a selective bottom-up deposition of conductive fill material to form a second source/drain contact. According to some of the methods, once the second source/drain contact has been formed, the contact plug may be formed over the gate stack.

公开(公告)号：US20230387221A1

公开(公告)日：2023-11-30

申请号：US18447053

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsien Huang ,  Chang-Ting Chung ,  Wei-Cheng Lin ,  Wei-Jung Lin ,  Chih-Wei Chang

IPC: H01L29/40 ,  H01L21/02 ,  H01L21/768 ,  H01L21/311 ,  H01L21/285 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/401 ,  H01L21/02238 ,  H01L21/76879 ,  H01L21/02164 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/28568 ,  H01L29/66795 ,  H01L21/02063 ,  H01L29/41791 ,  H01L21/76802 ,  H01L21/76826

Abstract: Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein. Methods include etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact and repairing silicon oxide structures along sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer to prevent selective loss defects from occurring during a subsequent selective deposition of conductive fill materials and during subsequent etching of other contact openings. The methods further include performing a selective bottom-up deposition of conductive fill material to form a second source/drain contact. According to some of the methods, once the second source/drain contact has been formed, the contact plug may be formed over the gate stack.

公开(公告)号：US20230386918A1

公开(公告)日：2023-11-30

申请号：US18360587

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsien Huang ,  Hong-Mao Lee ,  Hsien-Lung Yang ,  Yu-Kai Chen ,  Wei-Jung Lin

IPC: H01L21/768 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L21/76895 ,  H01L21/76807 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/665 ,  H01L29/7851 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76889 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871

Abstract: A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench.

公开(公告)号：US20230343712A1

公开(公告)日：2023-10-26

申请号：US18345388

申请日：2023-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Che Lin ,  Po-Yu Huang ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Feng-Yu Chang ,  Rueijer Lin ,  Wei-Jung Lin ,  Chen-Yuan Kao

IPC: H01L23/535 ,  H01L21/311 ,  H01L21/768 ,  H01L21/285 ,  H01L23/48 ,  H01L29/45 ,  H01L21/3213

CPC classification number: H01L23/535 ,  H01L21/28518 ,  H01L21/31116 ,  H01L21/32134 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/481 ,  H01L29/45

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

公开(公告)号：US11798843B2

公开(公告)日：2023-10-24

申请号：US17221958

申请日：2021-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Shih Wang ,  Chun-I Tsai ,  Shian Wei Mao ,  Ken-Yu Chang ,  Ming-Hsing Tsai ,  Wei-Jung Lin

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532 ,  H01L21/3213 ,  H01L23/485

CPC classification number: H01L21/76847 ,  H01L21/32134 ,  H01L21/76846 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.

公开(公告)号：US20210367042A1

公开(公告)日：2021-11-25

申请号：US17392320

申请日：2021-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsien Huang ,  Chang-Ting Chung ,  Wei-Cheng Lin ,  Wei-Jung Lin ,  Chih-Wei Chang

IPC: H01L29/40 ,  H01L21/02 ,  H01L21/768 ,  H01L21/311 ,  H01L21/285 ,  H01L29/66 ,  H01L29/417

Abstract: Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein. Methods include etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact and repairing silicon oxide structures along sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer to prevent selective loss defects from occurring during a subsequent selective deposition of conductive fill materials and during subsequent etching of other contact openings. The methods further include performing a selective bottom-up deposition of conductive fill material to form a second source/drain contact. According to some of the methods, once the second source/drain contact has been formed, the contact plug may be formed over the gate stack.

公开(公告)号：US10971396B2

公开(公告)日：2021-04-06

申请号：US16203918

申请日：2018-11-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Shih Wang ,  Chun-I Tsai ,  Shian Wei Mao ,  Ken-Yu Chang ,  Ming-Hsing Tsai ,  Wei-Jung Lin

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532 ,  H01L21/3213 ,  H01L23/485

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.

公开(公告)号：US20210098376A1

公开(公告)日：2021-04-01

申请号：US16984884

申请日：2020-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Che Lin ,  Po-Yu Huang ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Feng-Yu Chang ,  Rueijer Lin ,  Wei-Jung Lin ,  Chen-Yuan Kao

IPC: H01L23/535 ,  H01L29/45 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/285 ,  H01L21/768

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

公开(公告)号：US10535748B2

公开(公告)日：2020-01-14

申请号：US15909838

申请日：2018-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wen Cheng ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Hong-Mao Lee ,  Ming-Hsing Tsai ,  Sheng-Hsuan Lin ,  Wei-Jung Lin ,  Yan-Ming Tsai ,  Yu-Shiuan Wang ,  Hung-Hsu Chen ,  Wei-Yip Loh ,  Ya-Yi Cheng

IPC: H01L29/66 ,  H01L29/45 ,  H01L21/768 ,  H01L21/02 ,  H01L21/326 ,  H01L29/78 ,  H01L29/08 ,  H01L21/311 ,  H01L21/306 ,  H01L21/266 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/321

Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.