公开(公告)号：US5022007A

公开(公告)日：1991-06-04

申请号：US506616

申请日：1990-04-10

申请人： Kazutami Arimoto ,  Yoshio Matsuda ,  Tsukasa Ooishi ,  Masaki Tsukude ,  Kazuyasu Fujishima

发明人： Kazutami Arimoto ,  Yoshio Matsuda ,  Tsukasa Ooishi ,  Masaki Tsukude ,  Kazuyasu Fujishima

IPC分类号： G11C11/401 ,  G11C11/409 ,  G11C29/00 ,  G11C29/10 ,  G11C29/12 ,  G11C29/34 ,  G11C29/56

CPC分类号： G11C29/56 ,  G11C29/34

摘要： A test signal generator for a semiconductor integrated circuit memory, wherein when transfer transistors (20, 21, 14, 15) are rendered conductive, a test data cloumn is supplied from an I/O line pair (11, 12) to a column of a register (10) and stored therein. When a transfer (67) is rendered conductive, the test data column written in the register is written in a column of a memory cell (22) in the same pattern and when transfer transistors (16, 17) are rendered conductive, the test data column written in the register is inverted and the, written in the memory cell column, Data in the memory cell column is read out by a word line (13) and amplified by a sense amplifier (5), so that the data and the test data stored in the register are compared by a coincidence detection circuit 8 to detect whether it is coincident or not.

摘要翻译： 一种用于半导体集成电路存储器的测试信号发生器，其中当传输晶体管（20,21,14,15）导通时，测试数据线从I / O线对（11,12）提供到 寄存器（10）并存储在其中。 当传送（67）导通时，写入寄存器的测试数据列以相同的模式写入存储单元（22）的列中，并且当传输晶体管（16,17）导通时，测试数据 写入寄存器的列被反相，并且写入存储单元列中，存储单元列中的数据被字线（13）读出并由读出放大器（5）放大，使得数据和测试 存储在寄存器中的数据由重合检测电路8进行比较，以检测其是否一致。

公开(公告)号：US4982368A

公开(公告)日：1991-01-01

申请号：US463207

申请日：1990-01-10

申请人： Kazutami Arimoto

发明人： Kazutami Arimoto

IPC分类号： G11C11/401 ,  G11C5/02 ,  G11C7/06 ,  G11C7/18 ,  G11C8/14 ,  G11C11/4097 ,  G11C11/4099 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： G11C7/02 ,  G11C11/4097 ,  G11C11/4099 ,  G11C5/025 ,  G11C7/065 ,  G11C7/18 ,  G11C8/14

摘要： A dynamic semiconductor memory comprising memory cells arranged in a matrix of row and columns, a half of the memory cells being formed into sub-array #1 and the remaining half into sub-array #2. One of a plurality of bit lines included in sub-array #1 and one of a plurality of bit lines included in sub-array #2 constitute a bit line pair. Each of a plurality of word lines corresponding to the columns is divided into a first word line belonging to sub-array #1 and a second word line belonging to sub-array #2. When one of word lines is selected, a potential is applied to one of the first or second word line. As a result, when the information charge of a memory cell is output to certain bit line pair, a reading operation does not take place for the bit lines adjacent thereto, with the latter maintained at a predetermined potential. Thus, the bit line pair is free from the influence of noise due to a potential variation of the adjacent bit lines and the influence of the potential within the bit line pair itself.

摘要翻译： 一种动态半导体存储器，包括以行和列为矩阵排列的存储单元，一半存储单元形成子阵列＃1，剩余的一半形成子阵列＃2。 包括在子阵列＃1中的多个位线之一和子阵列＃2中包括的多个位线之一构成位线对。 对应于列的多个字线中的每一个被划分为属于子数组＃1的第一字线和属于子数组＃2的第二字线。 当选择一行字线时，将电位施加到第一或第二字线之一。 结果，当存储器单元的信息电荷被输出到某个位线对时，与其相邻的位线不会发生读取操作，而后者保持在预定电位。 因此，位线对由于相邻位线的电位变化和位线对内的电位的影响而不受噪声的影响。

公开(公告)号：US4910161A

公开(公告)日：1990-03-20

申请号：US237000

申请日：1988-08-26

申请人： Kazutami Arimoto

发明人： Kazutami Arimoto

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10844 ,  H01L27/10805

摘要： A semiconductor memory comprises a p.sup.- -type semiconductor substrate (1), a p-type epitaxial layer (15) and p.sup.+ -type epitaxial layers (16, 17) formed thereon, an n.sup.+ -type region (6) formed on the p.sup.+ -type epitaxial layer (16) to serve as a bit line, an n.sup.+ -type region (5) formed on the p.sup.+ -type epitaxial layer (17) to serve as a charge storage region and a gate electrode (9) formed on the p-type epitaxial layer (15) to serve as a word line. The p.sup.+ -type epitaxial layers (16, 17) prevent passage of electrons within electron-hole pairs induced by alpha rays, to suppress occurrence of soft errors. The p-type epitaxial layer (15) defines a region corresponding to the channel region of a bus transistor, whereby the impurity concentration thereof can be easily controlled, to readily set the threshold voltage of the bus transistor at an appropriate level.

公开(公告)号：US4788457A

公开(公告)日：1988-11-29

申请号：US94641

申请日：1987-09-09

申请人： Koichiro Mashiko ,  Kazutami Arimoto ,  Kiyohiro Furutani ,  Noriaki Matsumoto ,  Yoshio Matsuda

发明人： Koichiro Mashiko ,  Kazutami Arimoto ,  Kiyohiro Furutani ,  Noriaki Matsumoto ,  Yoshio Matsuda

IPC分类号： G11C11/408 ,  G11C8/10 ,  H03K17/693 ,  H03M7/00 ,  H03K19/096

CPC分类号： H03K17/693 ,  G11C8/10

摘要： A CMOS row decoder circuit in which a row decoder for selecting a single word line from a memory cell array and a column decoder for selecting a single bit line can use in common an internal address signal transmission line. The row decoder circuit comprises a series of MOSFETs of a first conductivity type which is turned on or off in response to address signals selected from external address signals, a second MOSFET of a second conductivity type provided between a power supply potential and the series of MOSFETs and having a gate receiving a first timing signal for providing decoding timing of the address signals, a third MOSFET of the first conductivity type provided between the series of MOSFETs and the second MOSFET and having a gate receiving a first operation timing signal, a fourth MOSFET which is turned on or off in response to a second operation timing signal for transmitting the potential of a node of the second MOSFET and the third MOSFET, and a fifth MOSFET having a gate receiving an output of the fourth MOSFET for transmitting a word line driving signal to a corresponding word line.

摘要翻译： 其中用于从存储单元阵列中选择单个字线的行解码器和用于选择单个位线的列解码器的CMOS行解码器电路可以共同地使用内部地址信号传输线。 行解码器电路包括响应于从外部地址信号中选择的地址信号而导通或截止的第一导电类型的一系列MOSFET，提供在电源电位和一系列MOSFET之间的第二导电类型的第二MOSFET 并且具有接收用于提供所述地址信号的解码定时的第一定时信号的栅极，设置在所述一系列MOSFET和所述第二MOSFET之间并具有接收第一操作定时信号的栅极的第一导电类型的第三MOSFET，第四MOSFET 其响应于用于传输第二MOSFET和第三MOSFET的节点的电位的第二操作定时信号而被接通或关断;以及第五MOSFET，其具有接收用于传输字线驱动的第四MOSFET的输出的栅极 信号到相应的字线。

公开(公告)号：US08188534B2

公开(公告)日：2012-05-29

申请号：US13022864

申请日：2011-02-08

申请人： Fukashi Morishita ,  Kazutami Arimoto

发明人： Fukashi Morishita ,  Kazutami Arimoto

IPC分类号： H01L29/788 ,  H01L27/01 ,  H01L27/12

CPC分类号： G11C11/405 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802

摘要： The present invention aims at providing a semiconductor memory device that can be manufactured by a MOS process and can realize a stable operation. A storage transistor has impurity diffusion regions, a channel formation region, a charge accumulation node, a gate oxide film, and a gate electrode. The gate electrode is connected to a gate line and the impurity diffusion region is connected to a source line. The storage transistor creates a state where holes are accumulated in the charge accumulation node and a state where the holes are not accumulated in the charge accumulation node to thereby store data “1” and data “0”, respectively. An access transistor has impurity diffusion regions, a channel formation region, a gate oxide film, and a gate electrode. The impurity diffusion region is connected to a bit line.

摘要翻译： 本发明的目的在于提供一种可以通过MOS工艺制造并可实现稳定操作的半导体存储器件。 存储晶体管具有杂质扩散区域，沟道形成区域，电荷累积节点，栅极氧化膜和栅电极。 栅电极连接到栅极线，杂质扩散区连接到源极线。 存储晶体管产生在电荷累积节点中积累空穴的状态和空穴未积累在电荷累积节点中的状态，从而分别存储数据“1”和数据“0”。 存取晶体管具有杂质扩散区，沟道形成区，栅极氧化膜和栅电极。 杂质扩散区域连接到位线。

公开(公告)号：US20110006806A1

公开(公告)日：2011-01-13

申请号：US12919356

申请日：2008-12-24

申请人： Kazutami Arimoto

发明人： Kazutami Arimoto

IPC分类号： H03K19/173

CPC分类号： H03K19/17756 ,  H03K19/1733

摘要： An ePLX unit includes a logic unit having an SRAM and a MUX, and a switch unit having an SRAM and a TG for establishing wiring connection in the logic unit. When a composite module is set in the first mode, an Add/Flag control unit uses the SRAMs as a data field and a flag field, respectively, to autonomously control the read address of each of the data field and the flag field in accordance with a control flag stored in the flag field. Furthermore, when the composite module is set in the second mode, the Add/Flag control unit writes configuration information into each of the SRAMs to reconfigure a logic circuit. Consequently, the granularity of the circuit configuration can be rendered variable, which allows improvement in flexibility when configuring a function.

摘要翻译： ePLX单元包括具有SRAM和MUX的逻辑单元，以及具有用于在逻辑单元中建立布线连接的SRAM和TG的开关单元。 当复合模块被设置为第一模式时，加法/标志控制单元分别使用SRAM作为数据字段和标志字段，以依照下述方式自主地控制每个数据字段和标志字段的读取地址 存储在标志字段中的控制标志。 此外，当复合模块被设置为第二模式时，加法/标志控制单元将配置信息写入每个SRAM以重新配置逻辑电路。 因此，电路配置的粒度可以变化，这允许在配置功能时提高灵活性。

公开(公告)号：US07652927B2

公开(公告)日：2010-01-26

申请号：US11797804

申请日：2007-05-08

申请人： Fukashi Morishita ,  Kazutami Arimoto

发明人： Fukashi Morishita ,  Kazutami Arimoto

IPC分类号： G11C16/06

CPC分类号： G11C7/14 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1048 ,  G11C11/405 ,  G11C11/4091 ,  G11C11/4099 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2207/2281 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/7841

摘要： When data “1” is stored in a memory cell, a bit line is driven to an H level (control line drive potential) and the other bit line is driven to an L level (reference potential) when a sense operation is completed. When a verify write operation is initiated, a charge line is driven from an H level (power supply potential) to an L level (reference potential). By the GIDL current from a source line, accumulation of holes is initiated again for a storage node subsequent to discharge of holes, whereby the potential of the storage node rises towards an H level (period α). When the charge line is driven to an H level from an L level, the potential of the storage node further rises (period β).

摘要翻译： 当数据“1”被存储在存储单元中时，当感测操作完成时，位线被驱动到H电平（控制线驱动电位），另一个位线被驱动到L电平（参考电位）。 当启动验证写操作时，充电线从H电平（电源电位）驱动到L电平（参考电位）。 通过来自源极线的GIDL电流，在空穴放电之后对于存储节点再次开始空穴累积，由此存储节点的电位向上升到H电平（周期α）。 当充电线从L电平驱动到H电平时，存储节点的电位进一步上升（周期β）。

公开(公告)号：US20090103353A1

公开(公告)日：2009-04-23

申请号：US12338219

申请日：2008-12-18

申请人： Kazutami Arimoto ,  Hiroki Shimano

发明人： Kazutami Arimoto ,  Hiroki Shimano

IPC分类号： G11C11/24 ,  G11C5/14 ,  G11C8/08

CPC分类号： G11C7/18 ,  G11C8/14 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4097 ,  G11C2211/4013 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/1085 ,  H01L27/10873 ,  H01L27/10882

摘要： Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.

摘要翻译： 构成存储单元板的导体线的导电线和构成存储单元板电极的导线被形成在包括多个存储单元的存储器件的同一互连层中，每个存储单元均包括用于以电荷形式存储数据的电容器。 通过将存储单元的电容器形成为平面电容器配置，由于电容器而导致的步骤被去除。 因此，可以通过CMOS工艺形成动态半导体存储器件，并且实现适合于与逻辑合并的动态半导体存储器件。 1位的数据由两个存储单元存储，即使由于平面型电容器而使存储单元的电容值减小，也可以可靠地存储数据。

公开(公告)号：US20080137394A1

公开(公告)日：2008-06-12

申请号：US12000343

申请日：2007-12-12

申请人： Hiroki Shimano ,  Fukashi Morishita ,  Kazutami Arimoto

发明人： Hiroki Shimano ,  Fukashi Morishita ,  Kazutami Arimoto

IPC分类号： G11C5/06

CPC分类号： G11C8/16 ,  G11C5/063 ,  G11C7/12 ,  G11C7/18 ,  G11C11/405 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/7841

摘要： One memory cell is formed of a first port access transistor, a second port access transistor and a storage transistor coupled commonly to these access transistors. The first port access transistor is coupled to a first electrode of the storage transistor, and the second port access transistor is coupled to a third electrode of the storage transistor. These first and second port access transistors enter a selected state when first and second port word lines are selected, respectively, to couple corresponding second and third electrodes of the corresponding storage transistor to first and second port bit lines, respectively. A dual-port memory cell of which scalability can follow miniaturization in a process can be provided.

摘要翻译： 一个存储单元由第一端口存取晶体管，第二端口存取晶体管和与这些存取晶体管共同耦合的存储晶体管形成。 第一端口存取晶体管耦合到存储晶体管的第一电极，第二端口存取晶体管耦合到存储晶体管的第三电极。 当分别选择第一和第二端口字线时，这些第一和第二端口存取晶体管进入选择状态，以将相应的存储晶体管的相应的第二和第三电极分别耦合到第一和第二端口位线。 可以提供一种双端口存储单元，其可扩展性可以在一个过程中跟随小型化。

公开(公告)号：US20070058407A1

公开(公告)日：2007-03-15

申请号：US11517441

申请日：2006-09-08

申请人： Katsumi Dosaka ,  Kazutami Arimoto ,  Kazunori Saito ,  Hideyuki Noda

发明人： Katsumi Dosaka ,  Kazutami Arimoto ,  Kazunori Saito ,  Hideyuki Noda

IPC分类号： G11C15/00

CPC分类号： G11C15/04 ,  G11C15/00

摘要： A CAM (Content Addressable Memory) cell includes first and second data storage portions storing data, horizontal port write gates for storing data applied through a match line pair in the data storage portions in a data write through a horizontal port, and search/read gates for driving the match lines of the match line pair in accordance with the data stored in the data storage portions in a search operation and in a data read through the horizontal port. The match lines are used as horizontal bit line pair, or signal lines for accessing the horizontal port. As the first and second data storage portions are used, it becomes possible to store ternary data, and accordingly, a write mask function of inhibiting a data write at a destination of data transfer is realized. Further, as the CAM cell is used, an arithmetic/logic operation following a search process can be executed selectively, and high speed data writing/reading becomes possible.

摘要翻译： CAM（内容可寻址存储器）单元包括存储数据的第一和第二数据存储部分，水平端口写入门，用于通过水平端口在数据存储部分中存储通过匹配线对应用的数据，以及搜索/读取门 用于根据搜索操作中存储在数据存储部分中的数据和通过水平端口读取的数据来驱动匹配线对的匹配线。 匹配线用作水平位线对或用于访问水平端口的信号线。 当使用第一和第二数据存储部分时，可以存储三进制数据，因此实现了在数据传送目的地禁止数据写入的写掩码功能。 此外，当使用CAM单元时，可以选择性地执行搜索处理之后的算术/逻辑运算，并且可以进行高速数据写入/读取。