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52 条记录 (耗时 0.026 秒)

    Semiconductor memory cell and semiconductor memory device
    41.
    发明授权
    Semiconductor memory cell and semiconductor memory device 失效
    半导体存储单元和半导体存储器件

    公开(公告)号：US06787832B2

    公开(公告)日：2004-09-07

    申请号：US10395457

    申请日：2003-03-24

    申请人： Günter Schmid ,  Marcus Halik ,  Hagen Klauk ,  Christine Dehm ,  Thomas Haneder ,  Thomas Mikolajick

    发明人： Günter Schmid ,  Marcus Halik ,  Hagen Klauk ,  Christine Dehm ,  Thomas Haneder ,  Thomas Mikolajick

    IPC分类号： H01L2976

    CPC分类号： B82Y10/00 ,  H01L21/28291 ,  H01L27/1159 ,  H01L29/6684

    摘要： A semiconductor memory cell has a field-effect transistor device and a ferroelectric storage capacitor. The field-effect transistor device has a channel region that includes or is made of an organic semiconductor material. Besides a first gate electrode of the gate electrode configuration of the field-effect transistor device, an additional selection gate electrode is provided, by way of which the field-effect transistor device can be switched off without influencing the storage dielectric and independently of the first gate electrode.

    摘要翻译： 半导体存储单元具有场效晶体管器件和铁电存储电容器。 场效应晶体管器件具有包含或由有机半导体材料制成的沟道区。 除了场效应晶体管器件的栅电极结构的第一栅电极之外，还提供附加的选择栅电极，通过该栅电极可以切断场效晶体管器件而不影响存储电介质，并且独立于第一栅电极 栅电极。

    Floating gate memory cell, method for fabricating it, and semiconductor memory device
    42.
    发明授权
    Floating gate memory cell, method for fabricating it, and semiconductor memory device 有权
    浮栅存储单元，其制造方法和半导体存储器件

    公开(公告)号：US06760252B2

    公开(公告)日：2004-07-06

    申请号：US10283913

    申请日：2002-10-30

    申请人： Thomas Mikolajick

    发明人： Thomas Mikolajick

    IPC分类号： G11C1604

    CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

    摘要： For particularly flexible and space-saving information storage, in the case of a floating gate memory cell and a corresponding semiconductor memory device, the invention includes providing a floating gate configuration with a plurality of floating gates. Each of the floating gates is configured for substantially independent information storage. As a result, a plurality of information units can be stored independently of one another in the memory cell.

    摘要翻译： 对于特别灵活和节省空间的信息存储，在浮动栅极存储器单元和对应的半导体存储器件的情况下，本发明包括提供具有多个浮动栅极的浮动栅极配置。 每个浮动门被配置为基本上独立的信息存储。 结果，可以在存储单元中彼此独立地存储多个信息单元。

    Integrated Circuits and Methods of Manufacturing Thereof
    43.
    发明申请
    Integrated Circuits and Methods of Manufacturing Thereof 有权
    集成电路及其制造方法

    公开(公告)号：US20080259687A1

    公开(公告)日：2008-10-23

    申请号：US11737617

    申请日：2007-04-19

    申请人： Michael Specht ,  Nicolas Nagel ,  Franz Hofmann ,  Thomas Mikolajick

    发明人： Michael Specht ,  Nicolas Nagel ,  Franz Hofmann ,  Thomas Mikolajick

    IPC分类号： G11C5/00 ,  H01R43/00

    CPC分类号： G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568 ,  Y10T29/49117

    摘要： Embodiments of the invention relate to integrated circuits having a memory cell arrangement and methods of manufacturing thereof. In one embodiment of the invention, an integrated circuit has a memory cell arrangement which includes a fin structure extending in its longitudinal direction as a first direction, including a first insulating layer, a first active region disposed above the first insulating layer, a second insulating layer disposed above the first active region, a second active region disposed above the second insulating layer, a charge storage layer structure disposed at least next to at least one sidewall of the fin structure covering at least a portion of the first active region and at least a portion of the second active region, and a control gate disposed next to the charge storage layer structure.

    摘要翻译： 本发明的实施例涉及具有存储单元布置的集成电路及其制造方法。 在本发明的一个实施例中，集成电路具有存储单元布置，其包括沿其纵向方向延伸的翅片结构作为第一方向，包括第一绝缘层，设置在第一绝缘层上方的第一有源区，第二绝缘层 设置在所述第一有源区上方的第二有源区，设置在所述第二绝缘层上方的第二有源区，电荷存储层结构，其至少布置在所述鳍结构的至少一个侧壁上，覆盖所述第一有源区的至少一部分，并且至少 第二有源区的一部分，以及设置在电荷存储层结构旁边的控制栅。

    Method for fabricating a semiconductor memory cell
    44.
    发明授权
    Method for fabricating a semiconductor memory cell 失效
    半导体存储单元的制造方法

    公开(公告)号：US07273786B2

    公开(公告)日：2007-09-25

    申请号：US11021626

    申请日：2004-12-22

    申请人： Thomas Mikolajick

    发明人： Thomas Mikolajick

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28273 ,  G11C16/0475 ,  H01L29/7887 ,  H01L29/7923

    摘要： In order to be able to store information in a non-volatile fashion as compactly and as flexibly as possible in a semiconductor memory cell, the original gate region of a conventional memory transistor is removed, and a memory gate configuration having a plurality of memory gates that are spatially separate from one another and that are electrically insulated with respect to one another is formed.

    摘要翻译： 为了能够在半导体存储单元中尽可能紧凑地且尽可能地灵活地存储非易失性的信息，去除了常规存储晶体管的原始栅极区域，并且具有多个存储器栅极的存储器栅极配置 在空间上彼此分离并且彼此相互电绝缘。

    Charge trapping memory cell and fabrication method
    47.
    发明授权
    Charge trapping memory cell and fabrication method 有权
    电荷捕获存储单元和制造方法

    公开(公告)号：US07227219B2

    公开(公告)日：2007-06-05

    申请号：US11055584

    申请日：2005-02-10

    申请人： Thomas Mikolajick

    发明人： Thomas Mikolajick

    IPC分类号： H01L29/76 ,  H01L21/8238

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： A memory cell patterned as a trench transistor is provided with a first gate electrode (4) as auxiliary gate for source-side injection and a second gate electrode (5) electrically insulated therefrom, which are arranged in the trench, and has, at the trench walls, a storage layer sequence (10) provided for charge trapping and comprising a storage layer (12) between boundary layers (11, 13). The first gate electrode (4) and the second gate electrode (5) are electrically insulated from one another, which can be effected by means of a portion of the storage layer sequence (10). Source/drain regions (3) are arranged on the top side laterally with respect to the trenches. Word lines (6), source/drain lines and control gate lines are present for the electrical driving.

    摘要翻译： 图案化为沟槽晶体管的存储单元设置有作为源侧注入的辅助栅极的第一栅电极（4）和与其电绝缘的第二栅电极（5），其布置在沟槽中，并且在 沟槽壁，用于电荷捕获的存储层序列（10），并且包括边界层（11,13）之间的存储层（12）。 第一栅电极（4）和第二栅电极（5）彼此电绝缘，这可以通过存储层序列（10）的一部分来实现。 源极/漏极区域（3）相对于沟槽横向设置在顶侧。 字线（6），源极/漏极线和控制栅极线用于电气驱动。

    Charge-trapping memory device and method of production
    48.
    发明授权
    Charge-trapping memory device and method of production 失效
    电荷俘获记忆装置及生产方法

    公开(公告)号：US07132337B2

    公开(公告)日：2006-11-07

    申请号：US11017194

    申请日：2004-12-20

    申请人： Stefan Jakschik ,  Matthias Goldbach ,  Thomas Mikolajick ,  Thomas Hecht

    发明人： Stefan Jakschik ,  Matthias Goldbach ,  Thomas Mikolajick ,  Thomas Hecht

    IPC分类号： H01L21/336

    CPC分类号： H01L29/512 ,  H01L21/28282 ,  H01L29/42348 ,  H01L29/78 ,  H01L29/7923

    摘要： Charge-trapping regions are arranged beneath lower edges of the gate electrode separate from one another. Source/drain regions are formed in self-aligned manner with respect to the charge-trapping regions by means of a doping process at low energy in order to form shallow junctions laterally extending only a small distance beneath the charge-trapping regions. The self-alignment ensures a large number of program-erase cycles with high effectiveness and good data retention, because the locations of the injections of charge carriers of opposite signs are narrowly and exactly defined.

    摘要翻译： 电荷捕获区域布置在栅电极的下边缘下方彼此分离。 源极/漏极区域以相对于电荷俘获区域的自对准方式通过在低能量下的掺杂工艺形成，以形成仅在电荷俘获区域下方仅小的距离的浅结。 自对准确保了大量的编程擦除周期，具有高效率和良好的数据保留，因为注入相反符号的电荷载体的位置被狭义地和精确地定义。