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    FIN-SHAPED STRUCTURE AND MANUFACTURING METHOD THEREOF
    42.
    发明申请
    FIN-SHAPED STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
    精细形状结构及其制造方法

    公开(公告)号：US20160071844A1

    公开(公告)日：2016-03-10

    申请号：US14512475

    申请日：2014-10-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jiun Shen ,  Ssu-I Fu ,  Yen-Liang Wu ,  Chia-Jong Liu ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Man-Ling Lu ,  Yi-Wei Chen

    IPC: H01L27/088 ,  H01L21/308 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/8236

    CPC classification number: H01L21/308 ,  H01L21/02238 ,  H01L21/30604 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66818

    Abstract: A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed.

    Abstract translation: 鳍状结构包括具有位于第一区域中的第一鳍状结构的基板和位于第二区域中的第二鳍状结构，其中第二鳍状结构包括梯形横截面轮廓部分 。 本发明还提供了形成该鳍状结构的两种方法。 在一种情况下，提供具有第一鳍状结构和第二鳍状结构的基板。 执行处理工艺以改变第二鳍状结构的顶部的外表面，从而形成修改部分。 进行去除处理以通过对第一鳍状结构和第二鳍状结构以及改性部分的高去除选择性去除改性部分，由此第二鳍状结构具有梯形横截面 形成轮廓部分。

    MOS TRANSISTOR AND SEMICONDUCTOR PROCESS FOR FORMING EPITAXIAL STRUCTURE
    44.
    发明申请
    MOS TRANSISTOR AND SEMICONDUCTOR PROCESS FOR FORMING EPITAXIAL STRUCTURE 审中-公开
    用于形成外延结构的MOS晶体管和半导体工艺

    公开(公告)号：US20160049496A1

    公开(公告)日：2016-02-18

    申请号：US14495907

    申请日：2014-09-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Man-Ling Lu ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Yen-Liang Wu ,  Wen-Jiun Shen ,  Chia-Jong Liu ,  Ssu-I Fu ,  Yi-Wei Chen

    IPC: H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/78

    CPC classification number: H01L29/66553 ,  H01L21/02057 ,  H01L21/0217 ,  H01L21/3086 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/78

    Abstract: A MOS transistor including a gate structure, an epitaxial spacer and an epitaxial structure is provided. The gate structure is disposed on a substrate. The epitaxial spacer is disposed on the substrate besides the gate structure, wherein the epitaxial spacer includes silicon and nitrogen, and the ratio of nitrogen to silicon is larger than 1.3. The epitaxial structure is disposed in the substrate besides the epitaxial spacer. A semiconductor process includes the following steps for forming an epitaxial structure. A gate structure is formed on a substrate. An epitaxial spacer is formed on the substrate besides the gate structure for defining the position of an epitaxial structure, wherein the epitaxial spacer includes silicon and nitrogen, and the ratio of nitrogen to silicon is larger than 1.3. The epitaxial structure is formed in the substrate besides the epitaxial spacer.

    Abstract translation: 提供了包括栅极结构，外延隔离物和外延结构的MOS晶体管。 栅极结构设置在基板上。 除了栅极结构之外，外延衬垫设置在衬底上，其中外延衬垫包括硅和氮，并且氮与硅之比大于1.3。 外延结构除了外延间隔物之外还设置在基板中。 半导体工艺包括用于形成外延结构的以下步骤。 在基板上形成栅极结构。 除了用于限定外延结构的位置的栅极结构之外，在衬底上形成外延衬垫，其中外延衬垫包括硅和氮，并且氮与硅之比大于1.3。 该外延结构除了外延间隔物外还形成在基板中。

    SEMICONDUCTOR DEVICE WITH EPITAXIAL STRUCTURE
    46.
    发明申请
    SEMICONDUCTOR DEVICE WITH EPITAXIAL STRUCTURE 有权
    具有外延结构的半导体器件

    公开(公告)号：US20150155386A1

    公开(公告)日：2015-06-04

    申请号：US14620209

    申请日：2015-02-12

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chung-Fu Chang ,  Cheng-Guo Chen ,  Chien-Ting Lin

    IPC: H01L29/78 ,  H01L29/161 ,  H01L29/06

    CPC classification number: H01L29/7851 ,  H01L21/8234 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7855

    Abstract: A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface, and the isolation structure at two sides of the gate structure has a second top surface. The first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure.

    Abstract translation: 半导体器件包括鳍结构，隔离结构，栅极结构和外延结构。 翅片结构从衬底的表面突出并且包括顶表面和两个侧壁。 隔离结构围绕翅片结构。 栅极结构覆盖鳍结构的一部分的顶表面和两个侧壁，并且覆盖隔离结构的一部分。 栅极结构下的隔离结构具有第一顶表面，并且栅极结构两侧的隔离结构具有第二顶表面。 第一顶面高于第二顶面。 外延层设置在栅极结构的一侧并与鳍结构直接接触。

    SEMICONDUCTOR PROCESS
    47.
    发明申请
    SEMICONDUCTOR PROCESS 有权
    半导体工艺

    公开(公告)号：US20140363935A1

    公开(公告)日：2014-12-11

    申请号：US13912218

    申请日：2013-06-07

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ssu-I Fu ,  Cheng-Guo Chen ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Chien-Ting Lin

    IPC: H01L29/66

    CPC classification number: H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848

    Abstract: A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate and a gate structure partially overlapping the fin-shaped structure is formed. Subsequently, a dielectric layer is blanketly formed on the substrate, and a part of the dielectric layer is removed to form a first spacer on the fin-shaped structure and a second spacer besides the fin-shaped structure. Furthermore, the second spacer and a part of the fin-shaped structure are removed to form at least a recess at a side of the gate structure, and an epitaxial layer is formed in the recess.

    Abstract translation: 半导体工艺包括以下步骤。 提供基板。 至少在基板上形成翅片状结构，形成与翅片状结构部分重叠的栅极结构。 随后，在衬底上覆盖地形成电介质层，除去电介质层的一部分，以在鳍状结构上形成第一间隔物，除了鳍状结构之外还形成第二间隔物。 此外，去除第二间隔件和鳍状结构的一部分以在栅极结构的一侧形成至少一个凹部，并且在凹部中形成外延层。

    Method of controlling etching process for forming epitaxial structure
    48.
    发明授权
    Method of controlling etching process for forming epitaxial structure 有权
    控制用于形成外延结构的蚀刻工艺的方法

    公开(公告)号：US08753902B1

    公开(公告)日：2014-06-17

    申请号：US13802494

    申请日：2013-03-13

    Applicant: United Microelectronics Corp.

    Inventor： Chia-Jong Liu ,  Yen-Liang Wu ,  Chung-Fu Chang ,  Yu-Hsiang Hung ,  Pei-Yu Chou ,  Home-Been Cheng

    IPC: G01R31/26

    CPC classification number: H01L21/31116 ,  H01L21/3065 ,  H01L21/3086 ,  H01L22/12 ,  H01L22/20 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

    Abstract: A method of controlling an etching process for forming an epitaxial structure includes the following steps. A substrate having a gate thereon is provided. A spacer is formed on the substrate beside the gate to define the position of the epitaxial structure. A thickness of the spacer is measured. The etching time of a first etching process is set according to the thickness. The first etching process is performed to form a recess in the substrate beside the spacer. The epitaxial structure is formed in the recess.

    Abstract translation: 控制用于形成外延结构的蚀刻工艺的方法包括以下步骤。 提供了具有栅极的基板。 在栅极旁边的衬底上形成间隔物以限定外延结构的位置。 测量间隔物的厚度。 第一蚀刻工艺的蚀刻时间根据厚度设定。 执行第一蚀刻工艺以在间隔物旁边的衬底中形成凹部。 在凹部中形成外延结构。

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