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公开(公告)号:US20210296572A1
公开(公告)日:2021-09-23
申请号:US17341417
申请日:2021-06-08
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Chen-Yi Weng , Yi-Wei Tseng , Chin-Yang Hsieh , Jing-Yin Jhang , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Yu-Ping Wang
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.
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公开(公告)号:US11087812B1
公开(公告)日:2021-08-10
申请号:US16931438
申请日:2020-07-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Yi-Hui Lee , I-Ming Tseng , Chiu-Jung Chiu , Chung-Liang Chu , Yu-Chun Chen , Ya-Sheng Feng , Yi-An Shih , Hsiu-Hao Hu , Yu-Ping Wang
Abstract: A MRAM includes a plurality of memory cells, an operation unit, a voltage generator, and an input/output circuit. The operation unit includes multiple groups of memory cells among the plurality of memory cells. The voltage generator is configured to provide a plurality of control signals by voltage-dividing a voltage control signal and selectively output the plurality of control signals to the input/output circuit. The input/output circuit is configured to output a plurality of switching pulse signals to the multiple groups of memory cells according to the plurality of control signals, wherein each switching pulse signal differs in pulse width or level.
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公开(公告)号:US10727397B1
公开(公告)日:2020-07-28
申请号:US16261524
申请日:2019-01-29
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Yi-Wei Tseng , Meng-Jun Wang , Chen-Yi Weng , Chin-Yang Hsieh , Jing-Yin Jhang , Yu-Ping Wang , Chien-Ting Lin , Ying-Cheng Liu , Yi-An Shih , Yi-Hui Lee , I-Ming Tseng
Abstract: A magneto-resistive random access memory (MRAM) cell includes a substrate having a dielectric layer disposed thereon, a conductive via disposed in the dielectric layer, and a cylindrical stack disposed on the conductive via. The cylindrical stack includes a bottom electrode, a magnetic tunneling junction (MTJ) layer on the bottom electrode, and a top electrode on the MTJ layer. A spacer layer is disposed on a sidewall of the cylindrical stack. The top electrode protrudes from a top surface of the spacer layer.
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公开(公告)号:US10475709B1
公开(公告)日:2019-11-12
申请号:US16030871
申请日:2018-07-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Fu-Jung Chuang , Ching-Ling Lin , Po-Jen Chuang , Yu-Ren Wang , Wen-An Liang , Chia-Ming Kuo , Guan-Wei Huang , Yuan-Yu Chung , I-Ming Tseng
IPC: H01L21/00 , H01L21/8238 , H01L27/092 , H01L21/762
Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to forma first trench; forming a dielectric layer in the first trench, wherein the dielectric layer comprises silicon oxycarbonitride (SiOCN); and planarizing the dielectric layer to form a first single diffusion break (SDB) structure.
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公开(公告)号:US09786502B2
公开(公告)日:2017-10-10
申请号:US15067157
申请日:2016-03-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Kuan-Hsien Li , Rai-Min Huang , I-Ming Tseng , Wen-An Liang , Chen-Ming Huang
IPC: H01L21/033 , H01L21/8234
CPC classification number: H01L21/0337 , H01L21/823431 , H01L21/845 , H01L29/6681
Abstract: A method for forming fin structure includes following steps. A substrate is provided. A first mandrel and a plurality of second mandrels are formed on the substrate simultaneously. A plurality of spacers are respectively formed on sidewalls of the first mandrel and the second mandrels and followed by removing the first mandrel and the second mandrels to form a first spacer pattern and a plurality of second spacer patterns. Then the substrate is etched to simultaneously form at least a first fin and a plurality of second fins on the substrate with the first spacer pattern and the second spacer patterns serving as an etching mask. At least one of the second fins is immediately next to the first fin, and a fin width of the first fin is larger than a fin width of the second fins. Then, the second fins are removed from the substrate.
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公开(公告)号:US20170263454A1
公开(公告)日:2017-09-14
申请号:US15067157
申请日:2016-03-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Kuan-Hsien Li , Rai-Min Huang , I-Ming Tseng , Wen-An Liang , Chen-Ming Huang
IPC: H01L21/033 , H01L21/8234
CPC classification number: H01L21/0337 , H01L21/823431 , H01L21/845 , H01L29/6681
Abstract: A method for forming fin structure includes following steps. A substrate is provided. A first mandrel and a plurality of second mandrels are formed on the substrate simultaneously. A plurality of spacers are respectively formed on sidewalls of the first mandrel and the second mandrels and followed by removing the first mandrel and the second mandrels to form a first spacer pattern and a plurality of second spacer patterns. Then the substrate is etched to simultaneously form at least a first fin and a plurality of second fins on the substrate with the first spacer pattern and the second spacer patterns serving as an etching mask. At least one of the second fins is immediately next to the first fin, and a fin width of the first fin is larger than a fin width of the second fins. Then, the second fins are removed from the substrate.
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公开(公告)号:US20170207129A1
公开(公告)日:2017-07-20
申请号:US15473614
申请日:2017-03-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: I-Ming Tseng , Wen-An Liang , Chen-Ming Huang
IPC: H01L21/8234 , H01L23/535 , H01L27/088 , H01L29/06 , H01L21/768 , H01L29/66
CPC classification number: H01L21/823475 , H01L21/76805 , H01L21/76895 , H01L21/823431 , H01L21/823481 , H01L23/485 , H01L23/535 , H01L27/0886 , H01L29/0649 , H01L29/0653 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/66515 , H01L29/66545 , H01L29/6681 , H01L29/7851
Abstract: The present invention further provides a method for forming a semiconductor device, comprising: first, a substrate having a fin structure disposed thereon is provided, wherein the fin structure has a trench, next, a first liner in the trench is formed, a first insulating layer is formed on the first liner, afterwards, a shallow trench isolation is formed in the substrate and surrounding the fin structure, wherein a bottom surface of the shallow trench isolation is higher than a bottom surface of the first insulating layer, and a top surface of the shallow trench isolation is lower than a top surface of the first insulating layer, and a dummy gate structure is formed on the first insulating layer and disposed above the trench, wherein a bottom surface of the dummy gate structure and a top surface of the fin structure are on a same level.
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公开(公告)号:US20170154823A1
公开(公告)日:2017-06-01
申请号:US14981929
申请日:2015-12-29
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: I-Ming Tseng , Wen-An Liang , Chen-Ming Huang
IPC: H01L21/8234 , H01L21/02 , H01L29/06 , H01L29/66 , H01L29/49 , H01L27/088 , H01L21/311
CPC classification number: H01L21/823481 , H01L21/0228 , H01L21/31105 , H01L21/823431 , H01L21/823437 , H01L21/82345 , H01L21/823456 , H01L27/0886 , H01L29/0649 , H01L29/0653 , H01L29/4966 , H01L29/66545 , H01L29/66795 , H01L29/785 , H01L29/7851
Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a first shallow trench isolation (STI) around the fin-shaped structure; dividing the fin-shaped structure into a first portion and a second portion; and forming a second STI between the first portion and the second portion.
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公开(公告)号:US09466691B2
公开(公告)日:2016-10-11
申请号:US14541107
申请日:2014-11-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: I-Ming Tseng , Rai-Min Huang , Tong-Jyun Huang , Kuan-Hsien Li , Chen-Ming Huang
IPC: H01L21/336 , H01L29/66 , H01L29/78 , H01L29/10 , H01L21/265
CPC classification number: H01L29/66537 , H01L21/26586 , H01L29/1041 , H01L29/66795 , H01L29/66803 , H01L29/785 , H01L29/7851
Abstract: A fin shaped structure and a method of forming the same, wherein the method includes forming a fin structure on a substrate. Next, an insulation layer is formed on the substrate and surrounds the fin structure, wherein the insulation layer covers a bottom portion of the fin structure to expose an exposed portion of the fin structure protruded from the insulation layer. Then, a buffer layer is formed on the fin structure. Following this, a threshold voltage implantation process is performed to penetrate through the buffer layer after forming the insulation layer, to form a first doped region on the exposed portion of the fin structure.
Abstract translation: 鳍状结构及其形成方法,其中,所述方法包括在基板上形成翅片结构。 接下来,在衬底上形成绝缘层并围绕鳍结构,其中绝缘层覆盖翅片结构的底部以暴露从绝缘层突出的鳍结构的暴露部分。 然后,在翅片结构上形成缓冲层。 接下来,在形成绝缘层之后,执行阈值电压注入工艺以穿透缓冲层,以在鳍结构的暴露部分上形成第一掺杂区域。
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公开(公告)号:US20160141387A1
公开(公告)日:2016-05-19
申请号:US14541107
申请日:2014-11-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: I-Ming Tseng , Rai-Min Huang , Tong-Jyun Huang , Kuan-Hsien Li , Chen-Ming Huang
IPC: H01L29/66 , H01L21/265 , H01L29/06 , H01L21/308 , H01L29/10 , H01L21/311 , H01L29/78 , H01L21/02
CPC classification number: H01L29/66537 , H01L21/26586 , H01L29/1041 , H01L29/66795 , H01L29/66803 , H01L29/785 , H01L29/7851
Abstract: A fin shaped structure and a method of forming the same, wherein the method includes forming a fin structure on a substrate. Next, an insulation layer is formed on the substrate and surrounds the fin structure, wherein the insulation layer covers a bottom portion of the fin structure to expose an exposed portion of the fin structure protruded from the insulation layer. Then, a buffer layer is formed on the fin structure. Following this, a threshold voltage implantation process is performed to penetrate through the buffer layer after forming the insulation layer, to form a first doped region on the exposed portion of the fin structure.
Abstract translation: 鳍状结构及其形成方法,其中,所述方法包括在基板上形成翅片结构。 接下来,在衬底上形成绝缘层并围绕鳍结构,其中绝缘层覆盖翅片结构的底部以暴露从绝缘层突出的鳍结构的暴露部分。 然后,在翅片结构上形成缓冲层。 接下来,在形成绝缘层之后,执行阈值电压注入工艺以穿透缓冲层,以在鳍结构的暴露部分上形成第一掺杂区域。
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