公开(公告)号：US12089508B2

公开(公告)日：2024-09-10

申请号：US17574569

申请日：2022-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chan Lin

IPC: H10N52/01 ,  H10B61/00 ,  H10N52/00 ,  H10N52/80

CPC classification number: H10N52/01 ,  H10B61/00 ,  H10N52/00 ,  H10N52/80

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic random access memory (MRAM) region and a logic region, forming a first inter-metal dielectric (IMB) layer on the substrate, forming a first metal interconnection and a second metal interconnection in the first IMD layer on the MRAM region, forming a spin orbit torque (SOT) layer on the first metal interconnection and the second metal interconnection, forming a magnetic tunneling junction (MTJ) stack on the SOT layer, forming a hard mask on the MTJ stack, using the hard mask to pattern the MTJ stack for forming the MTJ, forming the cap layer on the SOT layer and the hard mask, and patterning the cap layer and the SOT layer.

公开(公告)号：US20240203471A1

公开(公告)日：2024-06-20

申请号：US18108025

申请日：2023-02-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chan Lin ,  Jia-Rong Wu ,  Yi-Ting Wu

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/10

CPC classification number: G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H10B61/20 ,  H10N50/10

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region, a first gate pattern extending from the first cell region to the third cell region along a first direction, a first diffusion region extending from the first cell region to the second cell region along a second direction, a first metal pattern adjacent to one side of the first gate pattern and overlapping the first diffusion region, a source line pattern extending from the first cell region to the second cell region along the second direction, and a first spin orbit torque (SOT) pattern extending along the first direction and overlapping the first metal pattern and the source line pattern.

公开(公告)号：US20230084241A1

公开(公告)日：2023-03-16

申请号：US17500971

申请日：2021-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chan Lin ,  Yu-Ping Wang ,  Chien-Ting Lin

IPC: H01L43/14 ,  H01L27/22 ,  H01L43/04 ,  H01L43/06

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, forming an etch stop layer on the MTJ stack, forming a first spin orbit torque (SOT) layer on the etch stop layer, and then patterning the first SOT layer, the etch stop layer, and the MTJ stack to form a MTJ.

公开(公告)号：US20200243753A1

公开(公告)日：2020-07-30

申请号：US16850003

申请日：2020-04-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Chun Chen ,  Ya-Sheng Feng ,  Chiu-Jung Chiu ,  Hung-Chan Lin

IPC: H01L43/02 ,  H01L23/535 ,  H01L27/22 ,  H01L43/12 ,  G11C11/16 ,  H01L43/10

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the MTJ, and a second spacer on another side of the MTJ, in which the first spacer and the second spacer are asymmetric. Specifically, the MTJ further includes a first bottom electrode disposed on a metal interconnection, a capping layer on the bottom electrode, and a top electrode on the capping layer, in which a top surface of the first spacer is even with a top surface of the top electrode and a top surface of the second spacer is lower than the top surface of the top electrode and higher than the top surface of the capping layer.

公开(公告)号：US20200075840A1

公开(公告)日：2020-03-05

申请号：US16148852

申请日：2018-10-01

Applicant: United Microelectronics Corp.

Inventor： Ya-Sheng Feng ,  Yu-Chun Chen ,  Chiu-Jung Chiu ,  Hung-Chan Lin

IPC: H01L43/02 ,  G11C11/16 ,  H01F10/32 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L43/12 ,  H01L27/22 ,  H01F41/34

Abstract: A magnetoresistive memory cell is provided including a substrate. An inter-layer dielectric layer is disposed on the substrate. A via structure is disposed in the inter-layer dielectric layer. A magnetic pinned layer is disposed on the via structure. A tunnel barrier layer is disposed on the magnetic pinned layer to cover a top and a sidewall of the magnetic pinned layer, wherein the tunnel barrier layer comprises a horizontal extending portion outward from a bottom of the sidewall. A magnetic free layer with a -like structure is disposed on the tunnel barrier layer, wherein the magnetic free layer is isolated from the magnetic pinned layer by the tunnel bather layer. A spacer is disposed on the sidewall of the magnetic free layer. The spacer extends to the inter-layer dielectric layer.

公开(公告)号：US20190035674A1

公开(公告)日：2019-01-31

申请号：US15681419

申请日：2017-08-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chiu-Jung Chiu ,  Hung-Chan Lin ,  Yu-Chun Chen

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/768 ,  H01L29/94 ,  H01L27/06 ,  H01L49/02 ,  H01L21/8234 ,  H01L21/28

Abstract: An integrated circuit includes a first insulation layer, a bottom plate, a first patterned dielectric layer, a medium plate, a second patterned dielectric layer, and a top plate. The first patterned dielectric layer is disposed on the bottom plate. The medium plate is disposed on the first patterned dielectric layer. At least a part of the first patterned dielectric layer and the medium plate and a part of the bottom plate are disposed in a first trench penetrating the first insulation layer. The bottom plate, the first patterned dielectric layer, and the medium plate constitute a first metal-insulator-metal (MIM) capacitor. The second patterned dielectric layer is disposed on the medium plate. The top plate is disposed on the second patterned dielectric layer. The medium plate, the second patterned dielectric layer, and the top plate constitute a second MIM capacitor. The bottom plate is electrically connected with the top plate.

公开(公告)号：US10079277B2

公开(公告)日：2018-09-18

申请号：US15362771

申请日：2016-11-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tri-Rung Yew ,  Hung-Chan Lin ,  Li-Wei Feng ,  Chien-Ting Ho ,  Chia-Lung Chang

IPC: H01L21/20 ,  H01L49/02 ,  H01L21/311 ,  H01L21/3205 ,  H01L27/108

CPC classification number: H01L28/82 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32051 ,  H01L27/10852 ,  H01L28/87 ,  H01L28/91

Abstract: A method of fabricating a metal-insulator-metal capacitor includes providing a dielectric layer. The dielectric layer is etched to form a first hole including a first convex profile bulging into the dielectric layer. Subsequently, the dielectric layer is etched to form a second hole including a second convex profile bulging into the dielectric layer. A first metal layer is formed to conformally cover the capacitor trench. An insulating layer is formed to cover the first metal layer. Finally, a second metal layer is formed covering the insulating layer.

公开(公告)号：US20160187414A1

公开(公告)日：2016-06-30

申请号：US14585212

申请日：2014-12-30

Applicant: United Microelectronics Corp.

Inventor： Hung-Chan Lin

IPC: G01R31/26 ,  G01R27/02 ,  H01L21/66 ,  H01L29/788 ,  H01L27/088 ,  H01L29/10

CPC classification number: H01L27/0883 ,  H01L21/823431 ,  H01L21/845 ,  H01L22/14 ,  H01L22/34 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/1095

Abstract: A semiconductor device with FinFETs is provided, including a plurality of fin structures and a plurality of gate structures. The fin structures are disposed on a substrate, stretching along a first direction and spaced from each other by a first space. The fin structures comprise a selected fin structure. The gate structures are disposed on the substrate, stretching along a second direction. The gate structures comprise a first gate structure and a second gate structure which is adjacent to the first gate structure. A part of the selected fin structure and a part of the first gate structure form a first FinFET. A part of the selected fin structure and a part of the second gate structure form a second FinFET. The first FinFET is in depletion mode and the second FinFET is in enhancement mode. A method for measuring a resistance of FinFETs in a semiconductor device is provided.

Abstract translation: 提供了具有FinFET的半导体器件，其包括多个翅片结构和多个栅极结构。 翅片结构设置在基板上，沿着第一方向拉伸并且彼此间隔开第一空间。 翅片结构包括选定的翅片结构。 栅极结构设置在基板上，沿着第二方向拉伸。 栅极结构包括与第一栅极结构相邻的第一栅极结构和第二栅极结构。 所选翅片结构的一部分和第一栅极结构的一部分形成第一FinFET。 所选翅片结构的一部分和第二栅极结构的一部分形成第二FinFET。 第一个FinFET处于耗尽模式，第二个FinFET处于增强模式。 提供了一种用于测量半导体器件中的FinFET的电阻的方法。