公开(公告)号：US10049887B2

公开(公告)日：2018-08-14

申请号：US15678117

申请日：2017-08-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Chieh Hsu ,  Fu-Shou Tsai ,  Yu-Ting Li ,  Yi-Liang Liu ,  Kun-Ju Li

IPC: H01L21/3105 ,  H01L29/06 ,  H01L29/78

Abstract: A method of planarizing a substrate surface is disclosed. A substrate having a major surface of a material layer is provided. The major surface of the material layer comprises a first region with relatively low removal rate and a second region of relatively high removal rate. A photoresist pattern is formed on the material layer. The photoresist pattern masks the second region, while exposes at least a portion of the first region. At least a portion of the material layer not covered by the photoresist pattern is etched away. A polish stop layer is deposited on the material layer. A cap layer is deposited on the polish stop layer. A chemical mechanical polishing (CMP) process is performed to polish the cap layer.

公开(公告)号：US20180076205A1

公开(公告)日：2018-03-15

申请号：US15261845

申请日：2016-09-09

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yu-Ting Li ,  Jen-Chieh Lin ,  Wen-Chin Lin ,  Po-Cheng Huang ,  Fu-Shou Tsai

IPC: H01L27/108

CPC classification number: H01L27/10888 ,  H01L27/10823 ,  H01L27/10885 ,  H01L27/10894

Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

公开(公告)号：US20180033636A1

公开(公告)日：2018-02-01

申请号：US15221586

申请日：2016-07-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Chieh Hsu ,  Fu-Shou Tsai ,  Yu-Ting Li ,  Po-Cheng Huang ,  Yi-Liang Liu ,  Wen-Chin Lin ,  Chun-Yi Wang ,  Chun-Yuan Wu

IPC: H01L21/3105 ,  H01L21/02

CPC classification number: H01L21/31053 ,  H01L21/02065 ,  H01L21/32115 ,  H01L21/823431

Abstract: A method of fabricating a semiconductor structure is provided. A substrate surface is provided and a first layer is disposed on the substrate surface. A second layer covering the first layer is formed wherein the materials of the first layer and the second layer are different. A first polishing operation is performed on the second layer until a first polished surface exposing a portion of the first layer is obtained. A second polishing operation is performed on the first polished surface to obtain a second polished surface wherein an upper portion of the exposed portion of the first layer is removed. None of the substrate is exposed from the first polished surface and the second polished surface.

公开(公告)号：US20170162402A1

公开(公告)日：2017-06-08

申请号：US14960977

申请日：2015-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Shou Tsai ,  Yu-Ting Li ,  Li-Chieh Hsu ,  Kun-Ju Li ,  Chih-Hsun Lin ,  Po-Cheng Huang ,  Yi-Liang Liu ,  Wen-Chin Lin

IPC: H01L21/321 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L21/3212 ,  H01L21/0217 ,  H01L21/31053 ,  H01L21/7684

Abstract: A method of manufacturing a semiconductor structure is provided. First, a preliminary structure is provided. The preliminary structure has a first region and a second region, and the preliminary structure comprises a plurality of features in the first region. Then, a first polish stop layer is formed on the preliminary structure. The first polish stop layer comprises a concave portion in the second region, and the concave portion defines an opening. A first overlying layer is formed on the first polish stop layer. Thereafter, a second polish stop layer is formed on the first overlying layer. The second polish stop layer has a graduated change in composition. The second polish stop layer comprises a concave portion at least partially formed in the opening. A second overlying layer is formed on the second polish stop layer.

公开(公告)号：US20160268125A1

公开(公告)日：2016-09-15

申请号：US14656733

申请日：2015-03-13

Applicant: United Microelectronics Corp.

Inventor： Kun-Ju Li ,  Po-Cheng Huang ,  Yu-Ting Li ,  Jen-Chieh Lin ,  Chih-Hsun Lin ,  Tzu-Hsiang Hung ,  Wu-Sian Sie ,  I-Lun Hung ,  Wen-Chin Lin ,  Chun-Tsen Lu

IPC: H01L21/02 ,  H01L21/321 ,  H01L21/66 ,  H01L21/324

CPC classification number: H01L29/42364 ,  H01L21/02271 ,  H01L21/02354 ,  H01L21/02362 ,  H01L21/31051 ,  H01L21/3212 ,  H01L21/324 ,  H01L21/823437 ,  H01L22/12 ,  H01L22/20 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A semiconductor process includes the following steps. A dielectric layer is formed on a substrate, where the dielectric layer has at least a dishing from a first top surface. A shrinkable layer is formed to cover the dielectric layer, where the shrinkable layer has a second top surface. A treatment process is performed to shrink a part of the shrinkable layer according to a topography of the second top surface, thereby flattening the second top surface.

Abstract translation: 半导体工艺包括以下步骤。 电介质层形成在基板上，其中电介质层至少具有来自第一顶表面的凹陷。 形成可收缩层以覆盖电介质层，其中可收缩层具有第二顶表面。 执行处理过程以根据第二顶表面的形貌收缩可收缩层的一部分，从而使第二顶表面变平。

公开(公告)号：US09443726B1

公开(公告)日：2016-09-13

申请号：US14656733

申请日：2015-03-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Po-Cheng Huang ,  Yu-Ting Li ,  Jen-Chieh Lin ,  Chih-Hsun Lin ,  Tzu-Hsiang Hung ,  Wu-Sian Sie ,  I-Lun Hung ,  Wen-Chin Lin ,  Chun-Tsen Lu

IPC: H01L21/02 ,  H01L21/324 ,  H01L21/321 ,  H01L21/66

CPC classification number: H01L29/42364 ,  H01L21/02271 ,  H01L21/02354 ,  H01L21/02362 ,  H01L21/31051 ,  H01L21/3212 ,  H01L21/324 ,  H01L21/823437 ,  H01L22/12 ,  H01L22/20 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A semiconductor process includes the following steps. A dielectric layer is formed on a substrate, where the dielectric layer has at least a dishing from a first top surface. A shrinkable layer is formed to cover the dielectric layer, where the shrinkable layer has a second top surface. A treatment process is performed to shrink a part of the shrinkable layer according to a topography of the second top surface, thereby flattening the second top surface.

Abstract translation: 半导体工艺包括以下步骤。 电介质层形成在基板上，其中电介质层至少具有来自第一顶表面的凹陷。 形成可收缩层以覆盖电介质层，其中可收缩层具有第二顶表面。 执行处理过程以根据第二顶表面的形貌收缩可收缩层的一部分，从而使第二顶表面变平。

公开(公告)号：US09299600B2

公开(公告)日：2016-03-29

申请号：US14444131

申请日：2014-07-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Cheng Huang ,  Yu-Ting Li ,  Chih-Hsun Lin ,  Kun-Ju Li ,  Wu-Sian Sie ,  Yi-Liang Liu

IPC: H01L21/762 ,  H01L21/683 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/02227 ,  H01L21/02318 ,  H01L21/02348 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/6835 ,  H01L21/762 ,  H01L21/76229 ,  H01L21/76251 ,  H01L2221/68363 ,  H01L2221/68377 ,  H01L2221/68381

Abstract: A method for repairing an oxide layer and a method for manufacturing a semiconductor structure applying the same are provided. The method for repairing an oxide layer comprises following steps. First, a carrier having a first area and a second area is provided, wherein a repairing oxide layer is formed on the second area. Then, the carrier is attached to a substrate with an oxide layer to be repaired formed thereon, wherein the carrier and the substrate are attached to each other through the repairing oxide layer and the oxide layer to be repaired. Thereafter, the oxide layer to be repaired is bonded with the repairing oxide layer.

Abstract translation: 提供了修复氧化物层的方法和制造施加氧化物层的半导体结构体的方法。 修复氧化物层的方法包括以下步骤。 首先，提供具有第一区域和第二区域的载体，其中在第二区域上形成修复氧化物层。 然后，载体附着到其上形成有待修复的氧化物层的基板上，其中载体和基板通过修复氧化物层和待修复的氧化物层彼此附接。 此后，将要修复的氧化物层与修复氧化物层结合。

公开(公告)号：US09147612B2

公开(公告)日：2015-09-29

申请号：US14088445

申请日：2013-11-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Cheng Huang ,  I-Ming Tseng ,  Yu-Ting Li ,  Chun-Hsiung Wang ,  Wu-Sian Sie ,  Yi-Liang Liu ,  Chia-Lin Hsu ,  Po-Chao Tsao ,  Chien-Ting Lin ,  Shih-Fang Tzou

IPC: H01L21/338 ,  H01L21/8234 ,  H01L21/265

CPC classification number: H01L21/823431 ,  H01L21/265 ,  H01L21/3086 ,  H01L29/6681

Abstract: The present invention provides a manufacturing method for forming a semiconductor structure, in which first, a substrate is provided, a hard mask is disposed on the substrate, the hard mask is then patterned to form a plurality of fin hard masks and a plurality of dummy fin hard masks, afterwards, a pattern transferring process is performed, to transfer the patterns of the fin hard masks and the fin hard masks into the substrate, so as to form a plurality of fin groups and a plurality of dummy fins. Each dummy fin is disposed on the end side of one fin group, and a fin cut process is performed, to remove each dummy fin.

Abstract translation: 本发明提供一种用于形成半导体结构的制造方法，其中首先设置基板，在基板上设置硬掩模，然后将硬掩模图案化以形成多个散热片硬掩模和多个虚拟 翅片硬掩模，然后进行图案转印处理，将翅片硬掩模和翅片硬掩模的图案转移到基板中，以形成多个翅片组和多个虚拟翅片。 每个假翅片设置在一个翅片组的端侧，并进行翅片切割处理，以去除每个假翅片。

公开(公告)号：US20150214114A1

公开(公告)日：2015-07-30

申请号：US14166091

申请日：2014-01-28

Applicant: United Microelectronics Corp.

Inventor： Po-Cheng Huang ,  Yu-Ting Li ,  Wu-Sian Sie ,  Yi-Liang Liu ,  Chun-Hsiung Wang ,  Kun-Ju Li ,  Chia-Lin Hsu ,  Chih-Chien Liu

IPC: H01L21/8234 ,  H01L29/423 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/66 ,  H01L21/321

CPC classification number: H01L21/823437 ,  H01L21/31051 ,  H01L21/31055 ,  H01L29/66545

Abstract: A manufacturing method of a semiconductor structure is disclosed. The manufacturing method includes the following steps. A substrate with a plurality of dummy gate structures formed thereon and a first dielectric layer covering the dummy gate structures is provided, the dummy gate structures comprising a plurality of dummy gates and a plurality of insulating layers formed on the dummy gates, wherein at least two of the dummy gate structures have different heights. A first planarization process is performed to expose at least one of the dummy gate structures having the highest height. A first etching process is performed to expose the insulating layers. A chemical mechanical polishing (CMP) process with a non-selectivity slurry is performed to planarize the dummy gate structures. The planarized dummy gate structures are removed to form a plurality of gate trenches.

Abstract translation: 公开了一种半导体结构的制造方法。 该制造方法包括以下步骤。 提供具有形成在其上的多个虚拟栅极结构的基板和覆盖该虚拟栅极结构的第一介电层，所述伪栅极结构包括形成在所述伪栅极上的多个伪栅极和多个绝缘层，其中至少两个 的虚拟门结构具有不同的高度。 执行第一平面化处理以暴露具有最高高度的虚拟栅极结构中的至少一个。 执行第一蚀刻工艺以暴露绝缘层。 进行具有非选择性浆料的化学机械抛光（CMP）工艺以使虚拟栅极结构平坦化。 平面化的虚拟栅极结构被去除以形成多个栅极沟槽。