公开(公告)号：US20070091989A1

公开(公告)日：2007-04-26

申请号：US11583130

申请日：2006-10-19

申请人： Yoshiharu Kato ,  Yoshihiro Takemae ,  Toshio Ogawa ,  Tetsuhiko Endoh ,  Yoshinori Okajima

发明人： Yoshiharu Kato ,  Yoshihiro Takemae ,  Toshio Ogawa ,  Tetsuhiko Endoh ,  Yoshinori Okajima

IPC分类号： H04L5/16 ,  H04L25/00

CPC分类号： H04L25/0282 ,  H04L5/04 ,  H04L25/0294

摘要： Plural transmitter units generate plural currents corresponding to plural logical values, respectively, and propagate the currents to a common signal line. The common signal line synthesizes the currents generated by the transmitter units, and propagates them to a receiver unit as a synthetic current. The receiver unit restores the logical values the transmitter units generated, in accordance with the synthetic current. The values of the currents the transmitter units generate in correspondence with the logical values each differ, so that the value of the synthetic current can be changed for every combination of logical values. Accordingly, the receiver unit can restore the logical values outputted from the respective transmitter units, based on the synthetic current. That is, employing the common signal line enables signals transmitted from the transmitter units to be simultaneously received. Consequently, the number of signal lines laid between the transmitter units and the receiver unit is reduced.

摘要翻译： 多个发射机单元分别产生对应于多个逻辑值的多个电流，并将电流传播到公共信号线。 公共信号线合成由发射机单元产生的电流，并将其作为合成电流传播到接收机单元。 接收器单元根据合成电流恢复发射机单元产生的逻辑值。 发射机单元对应​​于逻辑值产生的电流值各自不同，使得可以针对逻辑值的每个组合来改变合成电流的值。 因此，接收机单元可以基于合成电流来恢复从各个发射机单元输出的逻辑值。 也就是说，采用公共信号线使得能够同时接收从发送单元发送的信号。 因此，放置在发射机单元和接收机单元之间的信号线的数量减少。

公开(公告)号：US20050242864A1

公开(公告)日：2005-11-03

申请号：US11055784

申请日：2005-02-11

申请人： Kenichi Kawasaki ,  Yasuharu Sato ,  Terumasa Kitahara ,  Masao Nakano ,  Masao Taguchi ,  Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Koichi Nishimura ,  Yoshinori Okajima ,  Naoharu Shinozaki ,  Hiroko Douchi

发明人： Kenichi Kawasaki ,  Yasuharu Sato ,  Terumasa Kitahara ,  Masao Nakano ,  Masao Taguchi ,  Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Koichi Nishimura ,  Yoshinori Okajima ,  Naoharu Shinozaki ,  Hiroko Douchi

IPC分类号： G06F13/42 ,  G11C7/10 ,  G11C7/22 ,  H03H11/26 ,  H03K5/00 ,  H03K5/13 ,  H03L7/081

CPC分类号： G11C7/106 ,  G06F13/4243 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/002 ,  G11C2207/108 ,  H03K5/133 ,  H03K2005/00058 ,  H03L7/0805 ,  H03L7/0814

摘要： Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.

摘要翻译： 公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。 该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路 输出定时，使得输出信号相对于外部时钟呈现给定的相位。 输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制 电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

公开(公告)号：US06333657B1

公开(公告)日：2001-12-25

申请号：US09518930

申请日：2000-03-03

申请人： Yoshinori Okajima

发明人： Yoshinori Okajima

IPC分类号： H03H1126

CPC分类号： H03H11/265 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00039 ,  H03L7/0812

摘要： A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.

摘要翻译： 受控延迟电路具有第一栅极链和第二栅极链。 第一栅极链用于测量第一控制信号的转换点和第二控制信号的转换点之间的时间差。 接收在第一门链中产生并表示时间差的第三信号的第二门链用于根据时间差从输入到输出提供适当的延迟时间。 受控延迟电路能够根据控制信号的周期适当地控制控制信号的定时。

公开(公告)号：US06194916B1

公开(公告)日：2001-02-27

申请号：US08869216

申请日：1997-06-04

申请人： Koichi Nishimura ,  Yoshinori Okajima

发明人： Koichi Nishimura ,  Yoshinori Okajima

IPC分类号： G01R2500

CPC分类号： G01R25/005

摘要： A phase comparator compares the phases of first and second signals with each other. The phase comparator has a first control circuit, a second control circuit, and a phase comparator unit. The first control circuit divides the frequency of the first signal by n in response to a third signal where n is an integer equal to or larger than 2. The second control circuit divides the frequency of the second signal by n in response to the third signal. The phase comparator unit compares the phases of signals provided by the first and second control circuits with each other. The phase comparator unit is capable of correctly comparing the phases of even high-speed signals with each other, and therefore, is applicable to a DLL circuit that operates on high-speed clock signals.

摘要翻译： 相位比较器将第一和第二信号的相位彼此进行比较。 相位比较器具有第一控制电路，第二控制电路和相位比较器单元。 第一控制电路响应于第三信号，其中n是等于或大于2的整数，将第一信号的频率除以n。第二控制电路响应于第三信号将第二信号的频率除以n 。 相位比较器单元将由第一和第二控制电路提供的信号的相位彼此进行比较。 相位比较器单元能够将偶数高速信号的相位彼此正确地进行比较，因此适用于对高速时钟信号进行动作的DLL电路。

公开(公告)号：US6151274A

公开(公告)日：2000-11-21

申请号：US440665

申请日：1999-11-16

申请人： Yoshihiro Takemae ,  Masao Taguchi ,  Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Hirohiko Mochizuki ,  Atsushi Hatakeyama ,  Yoshinori Okajima

发明人： Yoshihiro Takemae ,  Masao Taguchi ,  Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Hirohiko Mochizuki ,  Atsushi Hatakeyama ,  Yoshinori Okajima

IPC分类号： G06F13/42 ,  G06F1/10 ,  G06F1/12 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/4093 ,  H03K5/00 ,  H03K5/13 ,  H03K5/135 ,  H03L7/00 ,  H03L7/081 ,  H04L7/00 ,  G11C8/00

CPC分类号： H03L7/0805 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  H03K5/133 ,  H03K5/135 ,  H03L7/00 ,  H03L7/0814 ,  G11C2207/108

摘要： A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state. In the case where the skew between the input signals is small as compared with the skew between the input signals and the clock, an input timing adjusting circuit is shared by a plurality of the input circuits.

摘要翻译： 公开了一种用于实现这种系统的系统和半导体器件。 该系统至少使用半导体器件来与外部时钟产生的内部时钟同步地检索输入信号，该输入信号与外部时钟同步地保持有效。 即使在时钟与接收端的信号之间产生相位差的情况下，或者即使在时钟输入电路与接收端的半导体装置中的其他信号输入电路之间产生相位差的情况下，数据 可以高速转移。 在接收端的半导体器件的每个输入电路包括输入定时调整电路，用于调节施加到输入电路的时钟的相位，使得输入电路以有效和稳定的状态检索输入信号。 在输入信号与输入信号和时钟之间的偏差相比较小的情况下，输入定时调整电路被多个输入电路共享。

公开(公告)号：US6055615A

公开(公告)日：2000-04-25

申请号：US792134

申请日：1997-01-31

申请人： Yoshinori Okajima

发明人： Yoshinori Okajima

IPC分类号： G11C11/407 ,  G11C7/00 ,  G11C7/10 ,  G11C11/401 ,  G11C29/00 ,  G06F12/00

CPC分类号： G11C29/88 ,  G11C7/1015 ,  G11C7/1039 ,  G11C7/1072

摘要： A memory system using at least one DRAM chip and equipped with an interface for transferring input/output data in a packet format includes a plurality of banks within each of the at least one DRAM chip. The memory system further includes a control circuit for accessing a bank for data transfer of a given packet when the bank is different from a previous bank accessed for an immediately preceding packet, and for waiting for an operation to complete in the bank when the bank is the same as the previous bank.

摘要翻译： 使用至少一个DRAM芯片并配备有用于以分组格式传送输入/输出数据的接口的存储器系统包括在至少一个DRAM芯片的每一个内的多个存储体。 存储系统还包括一个控制电路，用于当银行与前一个分组所访问的前一个银行不同时，用于存取一个给定数据包的数据传输的存储单元，以及当银行是 与上一个银行相同。

公开(公告)号：US6028816A

公开(公告)日：2000-02-22

申请号：US924705

申请日：1997-09-05

申请人： Yoshihiro Takemae ,  Masao Taguchi ,  Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Hirohiko Mochizuki ,  Atsushi Hatakeyama ,  Yoshinori Okajima ,  Masao Nakano

发明人： Yoshihiro Takemae ,  Masao Taguchi ,  Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Hirohiko Mochizuki ,  Atsushi Hatakeyama ,  Yoshinori Okajima ,  Masao Nakano

IPC分类号： G06F13/42 ,  G06F1/10 ,  G06F1/12 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/4093 ,  H03K5/00 ,  H03K5/13 ,  H03K5/135 ,  H03L7/00 ,  H03L7/081 ,  H04L7/00 ,  G11C8/00

CPC分类号： H03L7/0805 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  H03K5/133 ,  H03K5/135 ,  H03L7/00 ,  H03L7/0814 ,  G11C2207/108

摘要： A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state. In the case where the skew between the input signals is small as compared with the skew between the input signals and the clock, an input timing adjusting circuit is shared by a plurality of the input circuits.

公开(公告)号：US5793680A

公开(公告)日：1998-08-11

申请号：US766173

申请日：1996-12-12

申请人： Yoshinori Okajima

发明人： Yoshinori Okajima

IPC分类号： G06F1/12 ,  G06F1/10 ,  G06F13/42 ,  G11C7/06 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  H03K5/00 ,  H03K19/0175 ,  G11C16/04 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/109 ,  G06F13/4243 ,  G11C7/06 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C7/225

摘要： An input buffer circuit includes a first amplifier causing a first change in an output signal by detecting a rising edge of an input signal, a second amplifier causing a second change in the output signal by detecting a falling edge of the input signal, and a feedback path feeding back the output signal as a feedback signal to the first amplifier and the second amplifier. The feedback signal controls the second amplifier such that a timing of the first change only depends on the first amplifier, and controls the first amplifier such that a timing of the second change only depends on the second amplifier.

摘要翻译： 输入缓冲电路包括：通过检测输入信号的上升沿来引起输出信号的第一变化的第一放大器;通过检测输入信号的下降沿引起输出信号的第二变化的第二放大器;以及反馈 路径将输出信号作为反馈信号反馈到第一放大器和第二放大器。 反馈信号控制第二放大器，使得第一变化的定时仅取决于第一放大器，并且控制第一放大器，使得第二变化的定时仅取决于第二放大器。

公开(公告)号：US5629645A

公开(公告)日：1997-05-13

申请号：US403945

申请日：1995-03-14

申请人： Yoshinori Okajima ,  Kazuyuki Kanazashi

发明人： Yoshinori Okajima ,  Kazuyuki Kanazashi

IPC分类号： G06F3/00 ,  G06F12/00 ,  G06F13/16 ,  G11C11/401 ,  H03K5/02 ,  H04L25/02 ,  H04L25/03 ,  H03K19/094

CPC分类号： H04L25/0264 ,  H04L25/03834

摘要： A transmission-line-voltage control circuit for controlling a level of a transmission line is disclosed. A signal of a first level indicating a logic high and a signal of a second level indicating a logic low are supplied to the transmission line. The transmission-line voltage control circuit includes a circuit connected to the transmission line. This circuit reduces, after the signal of the first level is supplied to the transmission line, the level of the transmission line to a third level which indicates the logic high and is less than the first level. And also the circuit increases, after the signal of the second level is supplied to the transmission line, the level of the transmission line to a fourth level which indicates the logic low and is higher than the second level.

摘要翻译： 公开了一种用于控制传输线的电平的传输线电压控制电路。 指示逻辑高的第一电平的信号和指示逻辑低的第二电平的信号被提供给传输线。 传输线电压控制电路包括连接到传输线的电路。 在将第一电平的信号提供给传输线之后，该电路将传输线的电平降低到指示逻辑高并且小于第一电平的第三电平。 并且在第二电平的信号被提供给传输线之后，电路也增加了传输线的电平到指示逻辑低并且高于第二电平的第四电平。

公开(公告)号：US5083294A

公开(公告)日：1992-01-21

申请号：US562512

申请日：1990-08-03

申请人： Yoshinori Okajima

发明人： Yoshinori Okajima

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C29/808

摘要： A semiconductor memory device having a plurality of main memory cell arrays, a redundant memory cell array, a plurality of word lines provided in each of the main memory cell arrays and the redundant memory cell array, a plurality of bit lines, a plurality of common word lines extending throughout the plurality of main memory cell arrays and the redundant memory cell array, a row decoder for addressing a common word line in response to first address data, a plurality of word line switches for selectively connecting the common word line to a corresponding word line, and a column decoder supplied with second address data for addressing a bit line in a main memory cell. The column decoder has a controller for selectively disabling the addressing of bit line in response to incoming of a particular combination of the second address data to the column decoder. A redundant column decoder is included which is supplied with second address data for selectively addressing a bit line in response to incoming of particular combination of the second address data. The word line switches for the redundant memory cell array are controlled such that the common word lines are connected to corresponding word lines of the redundant memory cell array irrespective of the first and second address data.