公开(公告)号：US08553452B2

公开(公告)日：2013-10-08

申请号：US13314470

申请日：2011-12-08

申请人： Yuchen Zhou ,  Ebrahim Abedifard ,  Yiming Huai

发明人： Yuchen Zhou ,  Ebrahim Abedifard ,  Yiming Huai

IPC分类号： G11C11/16

CPC分类号： G11C11/161 ,  G11C11/165

摘要： A testing method is described that applies a sequence external magnetic fields of varying strength to MRAM cells (such as those with MTJ memory elements) in chips or wafers to selectively screen out cells with low or high thermal stability factor. The coercivity (Hc) is used as a proxy for thermal stability factor (delta). In the various embodiments the sequence, direction and strength of the external magnetic fields is used to determine the high coercivity cells that are not switched by a normal field and the low coercivity cells that are switched by a selected low field. In some embodiment the MRAM's standard internal electric current can be used to switch the cells. Standard circuit-based resistance read operations can be used to determine the response of each cell to these magnetic fields and identify the abnormal high and low coercivity cells.

摘要翻译： 描述了一种测试方法，其将具有不同强度的序列外部磁场施加到芯片或晶片中的MRAM单元（例如具有MTJ存储元件的那些），以选择性地筛选具有低或高热稳定性因子的单元。 矫顽力（Hc）用作热稳定因子（delta）的代表。 在各种实施例中，外部磁场的顺序，方向和强度用于确定不被正常场切换的高矫顽力单元以及通过选定的低场切换的低矫顽力单元。 在一些实施例中，MRAM的标准内部电流可用于切换电池。 可以使用标准的基于电路的电阻读取操作来确定每个单元对这些磁场的响应并识别异常的高和低矫顽力单元。

公开(公告)号：US08758850B2

公开(公告)日：2014-06-24

申请号：US13238972

申请日：2011-09-21

申请人： Yuchen Zhou ,  Yiming Huai

发明人： Yuchen Zhou ,  Yiming Huai

IPC分类号： G11C15/02

CPC分类号： G11C11/161 ,  H01L43/12

摘要： A spin transfer torque magnetic random access memory (STTMRAM) element and a method of manufacturing the same is disclosed having a free sub-layer structure with enhanced internal stiffness. A first free sub-layer is deposited, the first free sub-layer being made partially of boron (B), annealing is performed of the STTMRAM element at a first temperature after depositing the first free sub-layer to reduce the B content at an interface between the first free sub-layer and the barrier layer, the annealing causing a second free sub-layer to be formed on top of the first free sub-layer and being made partially of B, the amount of B of the second free sub-layer being greater than the amount of B in the first free sub-layer. Cooling down the STTMRAM element to a second temperature that is lower than the first temperature and depositing a third free sub-layer directly on top of the second free layer, with the third free sub-layer being made partially of boron (B), wherein the amount of B in the third sub-free layer is less than the amount of B in the second free sub-layer.

摘要翻译： 公开了具有增强的内部刚度的自由子层结构的自旋转矩磁性随机存取存储器（STTMRAM）元件及其制造方法。 沉积第一自由子层，第一自由子层部分由硼（B）制成，在沉积第一自由子层之后，在第一温度下对STTMRAM元素进行退火，以降低B 在第一自由子层和阻挡层之间的界面，退火使第二自由子层形成在第一自由子层的顶部上并且部分地由B构成，第二自由子层的B的量 层大于第一自由子层中的B的量。 将STTMRAM元件冷却至低于第一温度的第二温度，并将第三自由子层直接沉积在第二自由层的顶部上，第三自由子层部分由硼（B）制成，其中 第三子自由层中的B的量小于第二自由子层中的B的量。

公开(公告)号：US08559215B2

公开(公告)日：2013-10-15

申请号：US13360524

申请日：2012-01-27

申请人： Yuchen Zhou ,  Yiming Huai

发明人： Yuchen Zhou ,  Yiming Huai

IPC分类号： G11C11/00

CPC分类号： G11C11/16 ,  G11C11/161 ,  G11C11/5607 ,  Y10S977/933 ,  Y10S977/935

摘要： A magnetic random access memory (MRAM) element is configured to store a state when electric current flows and includes a first magnetic tunnel junction (MTJ) for storing a data bit and a second MTJ for storing a reference bit. The direction of magnetization of the FL is determinative of the data bit stored in the at least one MTJ. Further, the MTJ includes a magnetic reference layer (RL) having a magnetization with a direction that is perpendicular to the film plane, and a magnetic pinned layer (PL) having a magnetization with a direction that is perpendicular to the film plane. The direction of magnetization of the RL and the PL are anti-parallel relative to each other in the first MTJ. The direction of magnetization of the FL, the RL and the PL are parallel relative to each other in the second MTJ.

摘要翻译： 磁性随机存取存储器（MRAM）元件被配置为存储电流流动时的状态，并且包括用于存储数据位的第一磁性隧道结（MTJ）和用于存储参考位的第二MTJ。 FL的磁化方向决定了存储在至少一个MTJ中的数据位。 此外，MTJ包括具有与膜平面垂直的方向的磁化的磁性参考层（RL）和具有与膜平面垂直的方向具有磁化的磁性固定层（PL）。 在第一MTJ中，RL和PL的磁化方向相对于彼此是反平行的。 在第二MTJ中，FL，RL和PL的磁化方向相对于彼此平行。

公开(公告)号：US20130194863A1

公开(公告)日：2013-08-01

申请号：US13546169

申请日：2012-07-11

申请人： Yuchen Zhou ,  Yiming Huai

发明人： Yuchen Zhou ,  Yiming Huai

IPC分类号： G11C11/16

CPC分类号： G11C11/16 ,  G11C11/161 ,  G11C11/5607 ,  G11C2013/0083 ,  Y10S977/933 ,  Y10S977/935

摘要： Methods using a sequence of externally generated magnetic fields to initialize the magnetization directions of each of the layers in perpendicular MTJ MRAM elements for data and reference bits when the required magnetization directions are anti-parallel are described. The coercivity of the fixed pinned and reference layers can be made unequal so that one of them can be switched by a magnetic field that will reliably leave the other one unswitched. Embodiments of the invention utilize the different effective coercivity fields of the pinned, reference and free layers to selectively switch the magnetization directions using a sequence of magnetic fields of decreasing strength. Optionally the chip or wafer can be heated to reduce the required field magnitude. It is possible that the first magnetic field in the sequence can be applied during an annealing step in the MRAM manufacture process.

公开(公告)号：US20120264234A1

公开(公告)日：2012-10-18

申请号：US13439817

申请日：2012-04-04

申请人： Yuchen Zhou ,  Yiming Huai

发明人： Yuchen Zhou ,  Yiming Huai

IPC分类号： H01L43/12

CPC分类号： H01L43/12 ,  B82Y40/00 ,  H01F10/3286 ,  H01F10/329 ,  H01F10/3295 ,  H01F41/307 ,  H01L43/10

摘要： A spin toque transfer magnetic random access memory (STTMRAM) element and a method of manufacturing the same is disclosed having a free sub-layer structure with enhanced internal stiffness. A first free sub-layer is deposited, the first free sub-layer being made partially of boron (B). Annealing is performed of the STTMRAM element at a first temperature after depositing the first free sub-layer to reduce the B content at an interface between the first free sub-layer and the barrier layer. Cooling down of the STTMRAM element to a second temperature that is lower than the first temperature is performed and a third free sub-layer is directly deposited on top of the second free layer, with the third free sub-layer being made partially of boron (B), wherein the amount of B in the third sub-free layer is less than the amount of B in the second free sub-layer.

摘要翻译： 公开了具有增强的内部刚度的自由子层结构的自旋转矩磁性随机存取存储器（STTMRAM）元件及其制造方法。 沉积第一自由子层，第一自由子层部分由硼（B）制成。 在沉积第一自由子层之后，在第一温度下对STTMRAM元件进行退火，以降低第一自由子层与势垒层之间的界面处的B含量。 执行STTMRAM元件的冷却到低于第一温度的第二温度，并且第三自由子层直接沉积在第二自由层的顶部上，第三自由子层部分地由硼制成（ B），其中第三子自由层中的B的量小于第二自由子层中的B的量。

公开(公告)号：US08704206B2

公开(公告)日：2014-04-22

申请号：US13356633

申请日：2012-01-23

申请人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang

发明人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang

IPC分类号： H01L29/06 ,  H01L47/00 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

摘要： The present invention relates to memory devices incorporating therein a novel memory cell architecture which includes an array of selection transistors sharing a common channel and method for making the same. A memory device comprises a semiconductor substrate having a first type conductivity, a plurality of drain regions and a common source region separated by a common plate channel in the substrate, and a selection gate disposed on top of the plate channel with a gate dielectric layer interposed therebetween. The plurality of drain regions and the common source region have a second type conductivity opposite to the first type provided in the substrate.

摘要翻译： 本发明涉及其中结合有新颖的存储单元架构的存储器件，其包括共享公共通道的选择晶体管阵列及其制造方法。 存储器件包括具有第一类型导电性的半导体衬底，多个漏极区域和由衬底中的公共板沟道分开的公共源极区域，以及选择栅极，其设置在板沟道的顶部，栅极介电层插入 之间。 多个漏极区域和公共源极区域具有与设置在衬底中的第一类型相反的第二类型导电性。

公开(公告)号：US20120306005A1

公开(公告)日：2012-12-06

申请号：US13136051

申请日：2011-07-21

申请人： Kimihiro Satoh ,  Jing Zhang ,  Yiming Huai

发明人： Kimihiro Satoh ,  Jing Zhang ,  Yiming Huai

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66795 ,  H01L29/7851

摘要： The present invention relates to transistor devices having a trough channel structure through which electrical current flows and methods for making the same. A transistor device having a semiconductor trough structure comprises a semiconductor substrate of a first conductivity type having a top surface; a semiconductor trough protruded from the top surface of the substrate along a first direction and having two top surfaces, two outer lateral surfaces, and an inner surface; a layer of isolation insulator disposed on the substrate and abutting the outer lateral surfaces of the semiconductor trough; a gate dielectric layer lining the inner surface and the top surfaces of the semiconductor trough; and a gate electrode disposed on top of the isolation insulator and extending over and filling the semiconductor trough with the gate dielectric layer interposed therebetween. The gate electrode extends along a second direction not parallel to the first direction provided in the semiconductor trough. Regions of the semiconductor trough not directly beneath the gate electrode have a second conductivity type opposite to the first conductivity type provided in the substrate.

摘要翻译： 本发明涉及具有通过电流流过的槽槽结构的晶体管器件及其制造方法。 具有半导体槽结构的晶体管器件包括具有顶表面的第一导电类型的半导体衬底; 半导体槽沿着第一方向从基板的顶表面突出并具有两个顶表面，两个外侧表面和内表面; 隔离绝缘层，设置在所述基板上并邻接所述半导体槽的外侧表面; 栅极电介质层，衬在半导体槽的内表面和顶表面上; 以及栅电极，其设置在隔离绝缘体的顶部并且延伸并填充半导体槽，栅介电层插入其间。 栅电极沿着不平行于半导体槽中的第一方向的第二方向延伸。 不直接在栅电极下方的半导体槽的区域具有与设置在基板中的第一导电类型相反的第二导电类型。

公开(公告)号：US20130056698A1

公开(公告)日：2013-03-07

申请号：US13225431

申请日：2011-09-03

申请人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang

发明人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang

IPC分类号： H01L45/00 ,  H01L21/8239

CPC分类号： H01L27/101 ,  H01L21/823487 ,  H01L27/105 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

摘要： The present invention relates to resistive memory devices incorporating therein vertical selection transistors and methods for making the same. A resistive memory device comprises a semiconductor substrate having a first type conductivity; a plurality of vertical selection transistors formed on the semiconductor substrate in an array, each of the plurality of vertical selection transistors including a semiconductor pillar protruded from the semiconductor substrate, top region of the semiconductor pillar having a second type conductivity opposite to the first type conductivity provided in the semiconductor substrate; and a gate electrode surrounding the semiconductor pillar with a gate dielectric layer interposed therebetween, the gate electrode being lower in height than the semiconductor pillar; a plurality of contact studs disposed on top of the vertical selection transistors; a plurality of resistive memory elements disposed on top of the contact studs; a plurality of parallel word lines connecting the vertical selection transistors by way of respective gate electrodes, the parallel word lines extending along a first direction; a plurality of parallel bit lines connecting the resistive memory elements, the parallel bit lines extending along a second direction different from the first direction provided in the parallel word lines; and a plurality of parallel source lines with the second type conductivity formed in top regions of the semiconductor substrate in between rows of the semiconductor pillars, wherein the source lines and the top regions of the semiconductor pillars function as source and drain, respectively.

摘要翻译： 本发明涉及结合有垂直选择晶体管的电阻式存储器件及其制造方法。 电阻式存储器件包括具有第一类型导电性的半导体衬底; 多个垂直选择晶体管，形成在阵列中的半导体衬底上，多个垂直选择晶体管中的每一个包括从半导体衬底突出的半导体柱，半导体柱的顶部区域具有与第一类型导电性相反的第二类型导电性 设置在半导体衬底中; 以及围绕所述半导体柱的栅电极，其间插入有栅极电介质层，所述栅电极的高度低于所述半导体柱; 设置在垂直选择晶体管顶部的多个接触柱; 设置在接触柱顶部的多个电阻性存储元件; 多个并行字线，通过相应的栅电极连接垂直选择晶体管，并行字线沿着第一方向延伸; 连接所述电阻性存储器元件的多条并行位线，所述并行位线沿着与所述并行字线中设置的第一方向不同的第二方向延伸; 以及在半导体柱的行之间分别形成有在半导体衬底的顶部区域中的具有第二类型导电体的多条平行的源极线，其中半导体柱的源极线和顶部区域分别用作源极和漏极。

公开(公告)号：US07284316B1

公开(公告)日：2007-10-23

申请号：US10991712

申请日：2004-11-17

申请人： Yiming Huai ,  Jinqiu Zhang ,  Jing Zhang

发明人： Yiming Huai ,  Jinqiu Zhang ,  Jing Zhang

IPC分类号： G11B5/127 ,  H04R31/00

CPC分类号： G11B5/3932 ,  B82Y10/00 ,  B82Y25/00 ,  G11B5/3163 ,  G11B2005/3996 ,  Y10T29/49034 ,  Y10T29/49043 ,  Y10T29/49046 ,  Y10T29/49048 ,  Y10T29/49052

摘要： A method for forming a hard bias structure in a magnetoresistive sensor is disclosed. A magnetoresistive sensor having a soft magnetic bias layer, spacer layer, and a magnetoresistive layer, is formed over a substrate having a gap layer. A mask is formed over a portion of the magnetoresistive sensor structure to define a central region. The masked structure is ion milled to remove portions not shielded by the mask, to form the central region with sloped sides, and to expose a region of the gap layer laterally adjacent the sloped sides. A first underlayer is deposited onto at least the sloped sides at a high deposition angle. A second underlayer is deposited to at least partially overlap the first underlayer, and at a first lower deposition angle. A hard bias layer is deposited over at least a portion of the second underlayer, and at a second lower deposition angle.

摘要翻译： 公开了一种在磁阻传感器中形成硬偏压结构的方法。 在具有间隙层的衬底上形成具有软磁偏置层，间隔层和磁阻层的磁阻传感器。 在磁阻传感器结构的一部分上形成掩模以限定中心区域。 被掩蔽的结构被离子研磨以去除未被掩模屏蔽的部分，以形成具有倾斜侧面的中心区域，并且使间隙层的区域横向暴露在倾斜侧面附近。 第一底层以高沉积角度沉积在至少倾斜的侧面上。 沉积第二底层至少部分地与第一底层重叠，并且以第一较低沉积角度沉积。 硬偏压层沉积在第二底层的至少一部分上，并且沉积在第二较低沉积角度。

公开(公告)号：US06989972B1

公开(公告)日：2006-01-24

申请号：US10261119

申请日：2002-09-30

申请人： Kroum Stoev ,  Mathew Gibbons ,  Francis Liu ,  Bogdan M. Simion ,  Aparna C. Vadde ,  Jing Zhang ,  Yiming Huai ,  Marcos M. Lederman

发明人： Kroum Stoev ,  Mathew Gibbons ,  Francis Liu ,  Bogdan M. Simion ,  Aparna C. Vadde ,  Jing Zhang ,  Yiming Huai ,  Marcos M. Lederman

IPC分类号： G11B5/39

CPC分类号： G11B5/3932

摘要： Magnetoresistive (MR) sensors have leads that overlap a MR structure and distribute current to the MR structure so that the current is not concentrated in small portions of the leads. An electrically resistive capping layer can be formed between the leads and the MR structure to distribute the current. The leads can include resistive layers and conductive layers, the resistive layers having a thickness-to-resistivity ratio that is greater than that of each of the conductive layers. The resistive layers may protect the conductive layers during MR structure etching, so that the leads have broad layers of electrically conductive material for connection to MR structures. The broad leads conduct heat better than the read gap material that they replace, further reducing the temperature at the connection between the leads and the MR structure.

摘要翻译： 磁阻（MR）传感器具有与MR结构重叠并且将电流分配到MR结构的引线，使得电流不集中在引线的小部分中。 可以在引线和MR结构之间形成电阻覆盖层以分布电流。 引线可以包括电阻层和导电层，电阻层的厚度 - 电阻率比大于每个导电层的厚度 - 电阻率比。 电阻层可以在MR结构蚀刻期间保护导电层，使得引线具有用于连接到MR结构的宽的导电材料层。 宽引线比它们所替代的读取间隙材料更好地传导热量，进一步降低引线与MR结构之间的连接处的温度。