公开(公告)号：US10796750B2

公开(公告)日：2020-10-06

申请号：US16031439

申请日：2018-07-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Igor Arsovski ,  Akhilesh Patil ,  Eric D. Hunt-Schroeder

IPC: G11C7/12 ,  G11C11/419 ,  G11C11/4074 ,  G11C11/4076

Abstract: The present disclosure relates to a structure including a sequential mode read controller which is configured to receive a sequential read enable burst signal and a starting word line address, identify consecutive read operations from an array of storage cells accessed via a plurality of word lines, precharge a plurality of bit lines of the storage cells no more than once during the consecutive read operations, and hold a word line of the word lines active throughout the consecutive read operations. The sequential read enable burst signal and a starting word line address are decoded to select a row address and activate the corresponding word line from a plurality of word lines in the array.

公开(公告)号：US10795430B1

公开(公告)日：2020-10-06

申请号：US16421730

申请日：2019-05-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Igor Arsovski ,  Kushal Kamal

IPC: G06F1/3296 ,  G06F30/00 ,  G05F3/20

Abstract: A semiconductor device is disclosed that includes, among other things, a computing device including a plurality of transistors, an activity monitor to determine an activity metric associated with the plurality of transistors, and a power controller to, responsive to the activity metric indicating a first activity level, set a power supply voltage for the plurality of transistors to a first value, and responsive to the activity metric indicating a second activity level less than the first activity level, set the power supply voltage to a second value greater than the first value and apply a first reverse back bias voltage to the plurality of transistors to increase a threshold voltage of the plurality of transistors.

公开(公告)号：US10790198B2

公开(公告)日：2020-09-29

申请号：US16058494

申请日：2018-08-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Fuad H. Al-Amoody ,  Yiheng Xu ,  Rishikesh Krishnan

IPC: H01L29/06 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to fin structures and methods of manufacture. The structure includes: a plurality of fin structures formed of substrate material; a semiconductor material located between selected fin structures of the plurality of fin structures; and isolation regions within spaces between the plurality of fin structures.

公开(公告)号：US10788877B1

公开(公告)日：2020-09-29

申请号：US16787520

申请日：2020-02-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sebastian T. Ventrone ,  Lansing D. Pickup

IPC: G06F1/32 ,  H03K3/037 ,  H03K17/00 ,  G06F1/04

Abstract: Embodiments of the disclosure provide a low power multiplexer (MUX) circuit, including: a first data input coupled to an input of a first pass gate device; a second data input coupled to an input of a second pass gate device; a hold latch having an input coupled to a data output of the MUX circuit and an output coupled to an input of a supplemental pass gate device; and a pulse generator for generating a HOLD pulse signal, wherein the HOLD pulse signal is coupled to a control input of the supplemental pass gate device. The hold latch is configured to hold a previously valid output data signal of the MUX circuit until a valid input data signal is available at the first data input or the second data input.

公开(公告)号：US10763342B2

公开(公告)日：2020-09-01

申请号：US16216356

申请日：2018-12-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Cheng Chi ,  Ruilong Xie

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/8234

Abstract: A method is presented for forming equal thickness gate spacers for a CMOS (complementary metal oxide semiconductor) device, the method includes forming a PFET (p-type field effect transistor) device and an NFET (n-type field effect transistor) device each including gate masks formed over dummy gates, forming PFET epi growth regions between the dummy gates of the PFET device, forming NFET epi growth regions between the dummy gates of the NFET device, depositing a nitride liner and an oxide over the PFET and NFET epi growth regions, the nitride liner and oxide extending up to the gate masks, and removing the dummy gates and the gate masks to form HKMGs (high-k metal gates) between the PFET and NFET epi growth regions.

公开(公告)号：US10763328B2

公开(公告)日：2020-09-01

申请号：US16151938

申请日：2018-10-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Omur Isil Aydin ,  Judson Holt ,  Lakshmanan Vanamurthy ,  Tobias Heyne ,  Pei-Yu Chou ,  Cäcilia Brantz

IPC: H01L29/08 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L21/02 ,  H01L21/265 ,  H01L29/167

Abstract: Structures for a field-effect transistor and methods for fabricating a structure for a field-effect transistor. A first epitaxial layer has a first surface and a second surface inclined relative to the first surface. A surface layer is arranged on the first and second surfaces of the first epitaxial layer. A second epitaxial layer is arranged over the surface layer on the first and second surfaces of the first epitaxial layer. A portion of the first epitaxial layer defines an interface with the surface layer. The portion of the first epitaxial layer contains a first concentration of a dopant. The surface layer contains a second concentration of the dopant that is greater than the first concentration of the dopant in the portion of the first epitaxial layer.

公开(公告)号：US10749031B2

公开(公告)日：2020-08-18

申请号：US15273778

申请日：2016-09-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, Inc. ,  STMICROELECTRONICS, INC.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L29/45 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/285

Abstract: A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein the bottom profile can be crafted to have a V-shape, U-shape, crescent shape, or other profile shape that includes at least a substantially sloped portion in the vertical direction. In one embodiment, the underlying layer is an epitaxial fin of a FinFET. A method of fabricating the low-resistance electrical contact employs a thin etch stop liner for use as a hard mask. The etch stop liner, e.g., HfO2, prevents erosion of an adjacent gate structure during the formation of the contact.

公开(公告)号：US10747254B1

公开(公告)日：2020-08-18

申请号：US16558599

申请日：2019-09-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sher Jiun Fang ,  See Taur Lee

IPC: G05F3/24 ,  H03K17/14 ,  G05F3/26

Abstract: The disclosure provides a circuit structure including a current source including at least one FDSOI transistor having a back-gate terminal, wherein the current source generates a current proportionate to an absolute temperature of the circuit structure; a first current mirror electrically coupled to the current source and a gate terminal of a device transistor, wherein the first current mirror applies a gate bias to the device transistor based on a magnitude of the current, and wherein a source or drain terminal of the device transistor includes an output current of the circuit structure; and an adjustable voltage source coupled to the back-gate terminal of the at least one FDSOI transistor of the current source, wherein the adjustable voltage source applies a selected back-gate bias voltage to the back-gate terminal of the at least one FDSOI transistor to adjust the current to compensate for process variations of the device transistor.

公开(公告)号：US10734525B2

公开(公告)日：2020-08-04

申请号：US15920886

申请日：2018-03-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Julien Frougier ,  Christopher M. Prindle ,  Nigel G. Cave

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423

Abstract: The disclosure relates to gate-all-around (GAA) transistors with a spacer support, and related methods. A GAA transistor according to embodiments of the disclosure includes: at least one semiconductor channel structure extending between a source terminal and a drain terminal; a spacer support having a first portion thereof positioned underneath and a second portion thereof positioned alongside a first portion of the at least one semiconductor channel structure; and a gate metal surrounding a second portion of the at least one semiconductor channel structure between the source and drain terminals; wherein the spacer support is positioned between the gate metal and the source or drain terminal.

公开(公告)号：US10734233B2

公开(公告)日：2020-08-04

申请号：US15902098

申请日：2018-02-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Guowei Xu ,  Keith Tabakman

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/49 ,  H01L23/535 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417

Abstract: In the manufacture of a FinFET device, an isolation architecture is provided between gate and source/drain contact locations. The isolation architecture may include a low-k spacer layer and a contact etch stop layer. The isolation architecture further includes a high-k, etch-selective layer that is adapted to resist degradation during an etch to open the source/drain contact locations. The high-k layer, in conjunction with a self-aligned contact (SAC) capping layer disposed over the gate, forms an improved isolation structure that inhibits short circuits or parasitic capacitance between the gate and source/drain contacts.