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    Flash Storage Controller Execute Loop
    41.
    发明申请
    Flash Storage Controller Execute Loop 有权
    Flash存储控制器执行循环

    公开(公告)号：US20140108715A1

    公开(公告)日：2014-04-17

    申请号：US14136549

    申请日：2013-12-20

    申请人： SanDisk Enterprise IP LLC

    发明人： Aaron K. Olbrich ,  Douglas A. Prins

    IPC分类号： G06F12/02

    CPC分类号： G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0246 ,  G06F13/1657 ,  G06F13/28 ,  G06F2212/7201 ,  G11C7/1051 ,  G11C7/1063 ,  G11C16/10

    摘要： A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously.

    摘要翻译： 提供了一个包含多个处理器的存储控制器。 在一些实施例中，存储控制器耦合到具有多个闪存组的闪速存储器模块，每个闪存组对应于存储控制器中的不同闪存端口，每个闪存端口包括相关联的处理器。 每个处理器处理一个或多个主机命令的一部分，包括读取和写入，允许多个并行流水线同时处理一个或多个主机命令。

    CROSS-PIPE SERIALIZATION FOR MULTI-PIPELINE PROCESSOR
    42.
    发明申请
    CROSS-PIPE SERIALIZATION FOR MULTI-PIPELINE PROCESSOR 有权
    多管道加工器的管道串联

    公开(公告)号：US20140095836A1

    公开(公告)日：2014-04-03

    申请号：US14101622

    申请日：2013-12-10

    申请人： International Business Machines Corporation

    发明人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Edward J. Kaminski ,  Diane L. Orf

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3836 ,  G06F9/3869 ,  G06F9/544 ,  G06F13/14 ,  G06F13/1605 ,  G06F13/1615 ,  G06F13/1621 ,  G06F13/1652 ,  G06F13/1657 ,  G06F13/1663

    摘要： Embodiments relate to cross-pipe serialization for a multi-pipeline computer processor. An aspect includes receiving, by a processor, the processor comprising a first pipeline, the first pipeline comprising a serialization pipeline, and a second pipeline, the second pipeline comprising a non-serialization pipeline, a request comprising a first subrequest for the first pipeline and a second subrequest for the second pipeline. Another aspect includes completing the first subrequest by the first pipeline. Another aspect includes, based on completing the first subrequest by the first pipeline, sending cross-pipe unlock signal from the first pipeline to the second pipeline. Yet another aspect includes, based on receiving the cross-pipe unlock signal by the second pipeline, completing the second subrequest by the second pipeline.

    摘要翻译： 实施例涉及用于多管线计算机处理器的跨管道串行化。 一个方面包括由处理器接收处理器，该处理器包括第一流水线，第一流水线包括串行化流水线和第二流水线，第二流水线包括非串行流水线，包括第一流水线的第一子请求的请求和 第二个管道的第二个子请求。 另一方面包括通过第一管道完成第一个子请求。 另一方面包括，基于通过第一管道完成第一子请求，将第一管道的跨管解锁信号发送到第二管道。 另一方面包括，基于通过第二管线接收横管解锁信号，通过第二管道完成第二子请求。

    STORAGE VIRTUALIZATION APPARATUS AND STORAGE VIRTUALIZATION METHOD
    44.
    发明申请
    STORAGE VIRTUALIZATION APPARATUS AND STORAGE VIRTUALIZATION METHOD 有权
    存储虚拟化设备和存储虚拟化方法

    公开(公告)号：US20140006725A1

    公开(公告)日：2014-01-02

    申请号：US13898541

    申请日：2013-05-21

    申请人： FUJITSU LIMITED

    发明人： Hiroshi Shiomi

    IPC分类号： G06F13/16

    CPC分类号： G06F13/1657 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/067 ,  H04L67/1097

    摘要： A storage virtualization apparatus includes: a first storing unit to store, with respect to each storage port, a process incomplete command count defined as number of commands not yet processed by the storage device having each storage port; a control unit to obtain process incomplete command counts accumulated by other storage virtualization apparatuses, and stores into a second storing unit a process incomplete command total count that is a total of the process incomplete command counts obtained from the other storage virtualization apparatuses and the first storing unit; and an access request responding unit to, when receiving an access request, obtain the process incomplete command total count about a storage port corresponding to the received access request, and to, when the obtained process incomplete command total count is larger than a prescribed number, cause completion timing of an access responding process to the access request to be delayed.

    摘要翻译： 存储虚拟化装置包括：第一存储单元，其针对每个存储端口存储定义为没有由具有每个存储端口的存储设备处理的命令的数量的处理不完整命令计数; 控制单元，其获取由其他存储虚拟化装置累积的处理不完整的命令计数，并将作为从其他存储虚拟化装置得到的处理不完整命令计数的总和的第一存储部分存储到第二存储单元中的处理不完整命令总计数 单元; 以及访问请求响应单元，当接收到访问请求时，获得关于与所接收的访问请求对应的存储端口的处理不完整命令总计数，并且当所获得的处理不完整命令总计数大于规定数量时， 使访问请求的访问响应处理的完成定时被延迟。

    Integer and half clock step division digital variable clock divider
    45.
    发明授权
    Integer and half clock step division digital variable clock divider 有权
    整数和半时钟分频数字可变时钟分频器

    公开(公告)号：US08598932B2

    公开(公告)日：2013-12-03

    申请号：US13888050

    申请日：2013-05-06

    申请人： Texas Instruments Incorporated

    发明人： Ramakrishnan Venkatasubramanian ,  Anthony Lell ,  Raguram Damodaran

    IPC分类号： G06F1/04 ,  H03K21/00

    CPC分类号： G06F12/1081 ,  G06F1/3296 ,  G06F7/483 ,  G06F9/3012 ,  G06F11/1064 ,  G06F12/0246 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/12 ,  G06F13/1605 ,  G06F13/1652 ,  G06F13/1657 ,  G06F13/1663 ,  G06F13/18 ,  G06F13/364 ,  G06F2212/1021 ,  G06F2212/1032 ,  G06F2212/221 ,  G06F2212/2532 ,  G06F2212/283 ,  G06F2212/608 ,  H03K19/0016 ,  H03K21/00 ,  H03M13/2903 ,  H03M13/353 ,  Y02D10/124 ,  Y02D10/172 ,  Y02D50/20

    摘要： A clock divider is provided that is configured to divide a high speed input clock signal by an odd, even or fractional divide ratio. The input clock may have a clock cycle frequency of 1 GHz or higher, for example. The input clock signal is divided to produce an output clock signal by first receiving a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates the divide ratio is N.5 when the fractional indicator is one and indicates the divide ratio is N when the fractional indicator is zero. F is set to 2(N.5)/2 for a fractional divide ratio and F is set to N/2 for an integer divide ratio. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd. One period of an output clock signal is synthesized in response to each assertion of the count indicator when the fractional indicator indicates the divide ratio is N.5. One period of the output clock signal is synthesized in response to two assertions of the count indicator when the fractional indicator indicates the divide ratio is an integer.

    摘要翻译： 提供了一个时钟分频器，其配置为将高速输入时钟信号除以奇数，偶数或分数分频比。 例如，输入时钟可以具有1GHz或更高的时钟周期频率。 输入时钟信号被分割以产生输出时钟信号，首先接收表示分频比N的除法因子值F，其中N可以是奇数或偶数整数。 分数指示符表示分数指示符为1时的分频比为N.5，当分数指示符为零时表示分频比为N。 对于分数除数，F被设置为2（N.5）/ 2，并且对于整数分频比，F被设置为N / 2。 当N为偶数时，每N / 2个输入时钟周期，计数指示器被置位。 当N为奇数时，计数指示灯交替显示N / 2个输入时钟周期，然后1 + N / 2个输入时钟周期。 当分数指示符表示分频比为N.5时，响应于计数指示符的每个断言，合成输出时钟信号的一个周期。 当分数指示符表示分频比是整数时，响应于计数指示符的两个断言，合成输出时钟信号的一个周期。

    COMPUTER SYSTEM AND METHOD FOR SHARING COMPUTER MEMORY
    47.
    发明申请
    COMPUTER SYSTEM AND METHOD FOR SHARING COMPUTER MEMORY 审中-公开
    用于共享计算机存储器的计算机系统和方法

    公开(公告)号：US20130132587A1

    公开(公告)日：2013-05-23

    申请号：US13813258

    申请日：2010-07-30

    申请人： Terrel Morris

    发明人： Terrel Morris

    IPC分类号： H04L29/08

    CPC分类号： H04L29/08171 ,  G06F13/1657 ,  H04L67/1008

    摘要： A computer system has a plurality of computer servers, each including at least one central processing unit (CPU). A memory appliance is spaced remotely from the plurality of computer servers. The memory appliance includes a memory controller and random access memory (RAM). At least one photonic interconnection is between the plurality of computer servers and the memory appliance. An allocated portion of the RAM is addressable by a predetermined CPU selected during a configuration event from the plurality of computer servers.

    摘要翻译： 计算机系统具有多个计算机服务器，每个计算机服务器包括至少一个中央处理单元（CPU）。 存储设备远离多个计算机服务器间隔开。 存储设备包括存储器控制器和随机存取存储器（RAM）。 在多个计算机服务器和存储设备之间至少有一个光子互连。 RAM的分配部分可由在多个计算机服务器的配置事件期间选择的预定CPU寻址。

    SYSTEMS AND METHODS FOR SHARING MEMORY BETWEEN A PLURALITY OF PROCESSORS
    49.
    发明申请
    SYSTEMS AND METHODS FOR SHARING MEMORY BETWEEN A PLURALITY OF PROCESSORS 审中-公开
    用于在大量处理器之间共享记忆的系统和方法

    公开(公告)号：US20120317356A1

    公开(公告)日：2012-12-13

    申请号：US13156845

    申请日：2011-06-09

    申请人： Michael Ignatowski

    发明人： Michael Ignatowski

    IPC分类号： G06F13/00

    CPC分类号： G06F13/1657 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007

    摘要： Systems and methods for sharing memory between a plurality of processors are provided. In one example, a shared memory system is disclosed. The system includes at least two processors and at least two memory devices, such as passive variable resistive memory (PVRM) devices. Each memory device is operatively connected to each processor via one of a plurality of processor interfaces. Each processor interface is dedicated to a single processor of the at least two processors. In this manner, any individual processor of the at least two processors is operative to access data stored in any individual memory device of the at least two memory devices via the processor interface dedicated to that respective individual processor.

    摘要翻译： 提供了用于在多个处理器之间共享存储器的系统和方法。 在一个示例中，公开了共享存储器系统。 该系统包括至少两个处理器和至少两个存储器件，诸如无源可变电阻存储器（PVRM）器件。 每个存储器设备经由多个处理器接口中的一个操作地连接到每个处理器。 每个处理器接口专用于至少两个处理器的单个处理器。 以这种方式，所述至少两个处理器的任何单独处理器可操作以经由专用于该相应单独处理器的处理器接口访问存储在至少两个存储器设备的任何单独存储器设备中的数据。