公开(公告)号：US20230369489A1

公开(公告)日：2023-11-16

申请号：US18317722

申请日：2023-05-15

申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

发明人： Huilong ZHU

IPC分类号： H01L29/78 ,  H01L21/225 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L23/522 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/3065 ,  H01L21/223 ,  H01L27/092

CPC分类号： H01L29/7848 ,  H01L21/2253 ,  H01L29/0653 ,  H01L29/42392 ,  H01L29/78642 ,  H01L29/78696 ,  H01L29/78618 ,  H01L23/5221 ,  H01L29/66545 ,  H01L21/823885 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/3065 ,  H01L21/2236 ,  H01L27/0925 ,  H01L29/7827 ,  H01L29/66666 ,  H01L27/092 ,  H01L21/823828 ,  H01L21/823814 ,  H01L21/823871

摘要： There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate, and a first device and a second device formed on the substrate. Each of the first device and the second device includes a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and also a gate stack surrounding a periphery of the channel layer. The channel layer of the first device and the channel layer of the second device are substantially co-planar.

公开(公告)号：US20230369461A1

公开(公告)日：2023-11-16

申请号：US18358909

申请日：2023-07-25

申请人： CHONGQING ALPHA AND OMEGA SEMICONDUCTOR LIMITED

发明人： FEI PENG ,  YI ZHAO ,  LIANG SHI

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L21/266

CPC分类号： H01L29/66666 ,  H01L29/4236 ,  H01L21/266

摘要： An SGT MOSFET device and a manufacturing method of contact holes of the SGT MOSFET device relate to a field of power semiconductor device manufacturing. The manufacturing method includes steps of preparing a gate trench, source trenches, a shielding gate trench, and a pre-embedded ESD trench, preparing a cell structure, preparing an ESD region, a body region, and a source region by ion implantation and preparing a gate contact hole, a source contact hole, a shield gate contact hole, and ESD contact holes. By pre-embedding an ESD structure, depth differences between the gate contact hole, the source contact hole, the shielding gate contact hole, and the ESD contact holes are reduced, and the contact holes are prepared by only one photolithography process. The manufacturing method reduces one photolithography process and one process of growing ESD polysilicon, saves cost, and reduces difficulty of the manufacturing process.

公开(公告)号：US20230363171A1

公开(公告)日：2023-11-09

申请号：US18353954

申请日：2023-07-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sheng-Chih Lai ,  Chung-Te Lin

IPC分类号： H10B51/20 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H10B51/30 ,  H10B51/40

CPC分类号： H10B51/20 ,  H01L29/78391 ,  H01L29/40111 ,  H01L29/66666 ,  H01L29/6684 ,  H01L29/7827 ,  H10B51/30 ,  H10B51/40

摘要： Various embodiments of the present disclosure are directed towards a metal-ferroelectric-insulator-semiconductor (MFIS) memory device, as well as a method for forming the MFIS memory device. According to some embodiments of the MFIS memory device, a lower source/drain region and an upper source/drain region are vertically stacked. A semiconductor channel overlies the lower source/drain region and underlies the upper source/drain region. The semiconductor channel extends from the lower source/drain region to the upper source/drain region. A control gate electrode extends along a sidewall of the semiconductor channel and further along individual sidewalls of the lower and upper source/drain regions. A gate dielectric layer and a ferroelectric layer separate the control gate electrode from the semiconductor channel and the lower and upper source/drain regions.

公开(公告)号：US20230326749A1

公开(公告)日：2023-10-12

申请号：US18203849

申请日：2023-05-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hung-Te Lin ,  Chia-Wei Liu ,  Hung Chih Yu

IPC分类号： H01L21/02 ,  H01L21/266 ,  H01L21/761 ,  H01L21/308

CPC分类号： H01L21/02496 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/266 ,  H01L21/308 ,  H01L21/761 ,  H01L29/66666

摘要： In a semiconductor manufacturing method, a mask is disposed on a semiconductor layer or semiconductor substrate. The semiconductor layer or semiconductor substrate is etched in an area delineated by the mask to form a cavity. With the mask disposed on the semiconductor layer or semiconductor substrate, the cavity is lined to form a containment structure. With the mask disposed on the semiconductor layer or semiconductor substrate, the containment structure is filled with a base semiconductor material. After filling the containment structure with the base semiconductor material, the mask is removed. At least one semiconductor device is fabricated in and/or on the base semiconductor material deposited in the containment structure.

公开(公告)号：US11784095B2

公开(公告)日：2023-10-10

申请号：US18087697

申请日：2022-12-22

申请人： Adeia Semiconductor Solutions LLC

发明人： Kangguo Cheng

IPC分类号： H01L21/8234 ,  H01L21/02 ,  H01L21/308 ,  H01L27/088 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L21/8238 ,  H01L21/266 ,  H01L21/762 ,  H10B10/00 ,  H10B12/00

CPC分类号： H01L21/823487 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/76232 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L27/088 ,  H01L29/0603 ,  H01L29/6681 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H10B10/12 ,  H10B12/36

摘要： A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.

公开(公告)号：US11777029B2

公开(公告)日：2023-10-03

申请号：US16455567

申请日：2019-06-27

申请人： Intel Corporation

发明人： Nazila Haratipour ,  I-Cheng Tung ,  Abhishek A. Sharma ,  Arnab Sen Gupta ,  Van Le ,  Matthew V. Metz ,  Jack Kavalieros ,  Tahir Ghani

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/7827 ,  H01L29/42364 ,  H01L29/66666

摘要： A vertical transistor structure includes a material stack having a source material, a drain material, and a channel material therebetween. The vertical transistor structure further includes a gate electrode adjacent to a sidewall of the stack, where the sidewall includes the channel material, and at least a partial thickness of both the source material and the drain material. A gate dielectric is present between the sidewall of the stack and the gate electrode. The vertical transistor structure further includes a first metallization over a first area of the stack above the gate dielectric layer, and in contact with the gate electrode on sidewall of the stack. A second metallization is adjacent to the first metallization, where the second metallization is over a second area of the stack, and in contact with the source material or the drain material.

公开(公告)号：US20230307543A1

公开(公告)日：2023-09-28

申请号：US18195480

申请日：2023-05-10

申请人： Micron Technology, Inc.

发明人： Hung-Wei Liu ,  Sameer Chhajed ,  Jeffery B. Hull ,  Anish A. Khandekar

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/04 ,  H10B12/00

CPC分类号： H01L29/7841 ,  H01L29/66666 ,  H01L29/7827 ,  H01L21/02686 ,  H01L29/04 ,  H10B12/20

摘要： A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 μm3 of one another. Other embodiments, including methods, are disclosed.

公开(公告)号：US11757001B2

公开(公告)日：2023-09-12

申请号：US17804491

申请日：2022-05-27

申请人： IceMos Technology Limited

发明人： Kiraneswar Muthuseenu ,  Samuel Anderson ,  Takeshi Ishiguro

IPC分类号： H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/265

CPC分类号： H01L29/0847 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7827 ,  H01L21/26513

摘要： A high voltage superjunction MOSFET includes a semiconductor substrate and a semiconductor layer having columns of first and second conductivity. A buffer layer of the first conductivity is between the semiconductor substrate and semiconductor layer. A plug region of the second conductivity is formed at a semiconductor layer surface and extends to the columns. A source/drain region is formed at the semiconductor layer surface and is connected to the plug region. The source/drain region has a concentration of the first conductivity between about 1×1019 cm−3 and 1.5×1020 cm−3. A body region of the second conductivity is between the source/drain region and the first column and is connected to the plug region. A gate trench is formed in the semiconductor layer surface and extends toward the first column and has a trench gate electrode disposed therein. A dielectric layer separates the trench gate electrode from the first column.

公开(公告)号：US11756957B2

公开(公告)日：2023-09-12

申请号：US17321563

申请日：2021-05-17

申请人： International Business Machines Corporation

发明人： Heng Wu ,  Chen Zhang ,  Kangguo Cheng ,  Tenko Yamashita ,  Joshua M. Rubin

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L21/84 ,  H01L29/66

CPC分类号： H01L27/088 ,  H01L21/84 ,  H01L29/6653 ,  H01L29/66666 ,  H01L29/7827

摘要： A semiconductor device structure and method for fabricating the same. The semiconductor device structure includes a first vertical transport field effect transistor (VTFET) comprising at least a first gate structure having a first gate length, and a second VTFET stacked on the first VTFET and comprising at least a second gate structure having a second gate length that is less than the first gate length. The method includes forming, on a substrate, a first VTFET including at least a first gate structure having a first gate length. The method further includes forming a second VTFET stacked on the first VTFET and including at least a second gate structure having a second gate length that is less than the first gate length.

公开(公告)号：US11742246B2

公开(公告)日：2023-08-29

申请号：US17502210

申请日：2021-10-15

申请人： International Business Machines Corporation

发明人： Ruilong Xie ,  Hemanth Jagannathan ,  Christopher J. Waskiewicz ,  Alexander Reznicek

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

CPC分类号： H01L21/823481 ,  H01L21/76224 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/7827

摘要： A vertical field effect transistor structure and method for fabricating the same. The structure includes a source/drain layer in contact with at least one semiconductor fin. An edge portion of the source/drain layer includes a notched region filled with a dielectric material. A spacer layer includes a first portion in contact with the source/drain layer and a second portion in contact with the dielectric material. A gate structure contacts the spacer layer and the dielectric material. The method includes forming a source/drain layer in contact with at least one semiconductor fin. A spacer layer is formed in contact with the source/drain layer. A portion of the spacer layer is removed to expose an end portion of the source/drain layer. The exposed end portion of the source/drain layer is recessed to form a notched region within the source/drain layer. A dielectric layer is formed within the notched region.