公开(公告)号：US20180102477A1

公开(公告)日：2018-04-12

申请号：US15426719

申请日：2017-02-07

申请人： Korea Advanced Institute of Science and Technology

发明人： Yang-Kyu Choi ,  Jun-Young Park ,  Chang-Hoon Jeon

IPC分类号： H01L45/00 ,  H01L29/06 ,  H01L29/423 ,  H03K17/687

CPC分类号： H01L45/1206 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L35/00 ,  H01L45/1226 ,  H03K17/687

摘要： Provided is a method for increasing a driving current of a junctionless transistor that includes: a substrate; a source region and a drain region which are formed on the substrate and are doped with the same type of dopant; a nanowire channel region which connects the source region and the drain source and is doped with the same type dopant as that of the source region and the drain region; a gate insulation layer which is formed to surround the nanowire channel region; and a gate electrode which is formed on the gate insulation layer and is formed to surround the nanowire channel region. An amount of current flowing through the nanowire channel region is increased by joule heat generated by applying a voltage to the source region and the drain region.

公开(公告)号：US09941421B2

公开(公告)日：2018-04-10

申请号：US14922123

申请日：2015-10-24

申请人： Helios Focus LLC

发明人： Randy R. Dunton ,  Geoffrey Sutton

IPC分类号： H01H47/00 ,  H01L31/02 ,  H03K17/795 ,  H03K17/687 ,  H02S50/00 ,  H02S40/32 ,  H02S40/34

CPC分类号： H01L31/02021 ,  H02S40/32 ,  H02S40/34 ,  H02S50/00 ,  H03K17/687 ,  H03K17/7955 ,  Y10T307/76

摘要： A photovoltaic (PV) module safety shutdown system includes a module-on switch coupled with a PV module coupled with an alternating current (AC) mains panel through an inverter. A system monitor couples with the module-on switch and with the AC mains panel and generates a system-on signal. A module discharge switch couples with an inherent capacitance of the inverter and with the system monitor. The module discharge switch discharges the inherent capacitance, by coupling the inherent capacitance with a discharge element, in response to the system monitor not generating the system-on signal. In implementations a module short switch shorts the PV module in response to a passage of a predetermined amount of time after the module discharge switch is switched on. The module-on switch, module discharge switch, and module short switch may be included in a junction box of the PV module and coupled with the system monitor through multiple opto-isolators.

公开(公告)号：US09935113B2

公开(公告)日：2018-04-03

申请号：US15604672

申请日：2017-05-25

申请人： eMemory Technology Inc.

发明人： Meng-Yi Wu ,  Hsin-Ming Chen

IPC分类号： H01L27/112 ,  H01L29/78 ,  H01L23/525 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/16 ,  H01L29/423 ,  G11C17/16 ,  G11C17/18

CPC分类号： H02M3/07 ,  G11C5/145 ,  G11C5/147 ,  G11C7/06 ,  G11C7/062 ,  G11C7/065 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C11/419 ,  G11C17/165 ,  G11C17/18 ,  G11C2207/002 ,  H01L23/5252 ,  H01L27/11206 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/7848 ,  H01L29/7851 ,  H02M2003/075 ,  H03K3/012 ,  H03K5/134 ,  H03K5/159 ,  H03K17/687 ,  H03K2005/00195

摘要： A non-volatile memory (NVM) includes a fin structure, a first fin field effect transistor (FinFET), a second FinFET, an antifuse structure, a third FinFET, and a fourth FinFET. The antifuse structure is formed on the fin structure and has a sharing gate, a single diffusion break (SDB) isolation structure, a first source/drain region, and a second source/drain region. The SDB isolation structure isolates the first source/drain region and the second source/drain region. The first FinFET, the second FinFET and the first antifuse element compose a first one time programmable (OTP) memory cell, and the third FinFET, the fourth FinFET and the second antifuse element compose a second OTP memory cell. The first OTP memory cell and the second OTP memory cell share the antifuse structure.

公开(公告)号：US20180083551A1

公开(公告)日：2018-03-22

申请号：US15448288

申请日：2017-03-02

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Yuichi GOTO ,  Hiroshi MOCHIKAWA

IPC分类号： H02M7/5387 ,  H02P6/08

CPC分类号： H02M7/5387 ,  H02M2001/0051 ,  H02P6/085 ,  H02P7/28 ,  H03K17/687 ,  H03K17/74 ,  H03K2217/0036 ,  H03K2217/0045 ,  Y02B70/1491

摘要： A power conversion device includes a first switch and a second switch connected in series between a positive electrode and a negative electrode of a first power supply. A first node is between the first and second switches. The first node can be connected to a load. A first diode has an anode connected to the first node and a cathode connected to the positive electrode of the first power supply. A third switch is connected between a positive electrode of a second power supply and the positive electrode of the first power supply. A first timer is connected to a gate electrode of the third switch. A first comparator has a first input that is connected to a gate electrode of the first switch, a second input at which a reference voltage can be received, and an output that is connected to the first timer.

公开(公告)号：US09923559B2

公开(公告)日：2018-03-20

申请号：US14829938

申请日：2015-08-19

申请人： Monterey Research, LLC

发明人： David G. Wright ,  Jason Faris Muriby ,  Erhan Hancioglu

IPC分类号： H03K3/00 ,  H03K17/687 ,  H03K19/003 ,  H03K19/00

CPC分类号： H03K17/687 ,  H03K19/0016 ,  H03K19/00369

摘要： A method for driving a load includes driving a load to an initial voltage within a voltage window, the voltage window based on an input voltage and an offset voltage, and driving the load to approximately the input voltage.

公开(公告)号：US09917507B2

公开(公告)日：2018-03-13

申请号：US14724067

申请日：2015-05-28

申请人： SanDisk Technologies LLC

发明人： Gooty Sukumar Reddy ,  Potnuru Venkata Pradeep Kumar ,  Sridhar Yadala

IPC分类号： H03K3/03 ,  H02M3/07 ,  H03K3/354 ,  H02M1/44 ,  H02M1/08 ,  H03K17/687 ,  H02M3/00 ,  H03L7/18 ,  H03K3/0231 ,  H02M1/00

CPC分类号： H02M3/07 ,  H02M1/08 ,  H02M1/44 ,  H02M3/00 ,  H02M2001/0003 ,  H03K3/0231 ,  H03K3/354 ,  H03K17/687 ,  H03L7/18

摘要： A charge pump is connected to receive a supply voltage and a clock signal and generate an output voltage. The charge pump is connected to the supply voltage through a transistor whose gate voltage is set by a regulation voltage determined by feedback from the output voltage. The current supplied to the charge pump through this transistor is mirrored in a section that generates the clock signal, where the mirrored current is used by a current controller oscillator. This allows the pump's clock frequency to linearly track the load current, improving the pump's efficiency.

公开(公告)号：US09912331B2

公开(公告)日：2018-03-06

申请号：US15686161

申请日：2017-08-25

申请人： IXYS Corporation

发明人： Andreas Laschek-Enders

IPC分类号： H03K3/00 ,  H03K17/567 ,  H03K5/14 ,  H03K17/687 ,  H01L27/06 ,  H01L29/739 ,  H03K5/00

CPC分类号： H03K17/567 ,  H01L27/0629 ,  H01L27/0647 ,  H01L29/7393 ,  H03K5/14 ,  H03K17/166 ,  H03K17/687 ,  H03K2005/00058

摘要： A gate driver integrated circuit for driving a gate of an IGBT or MOSFET receives an input signal. In response to a rising edge of the input signal, the integrated circuit causes the gate to be driven in a first sequence of time periods. In each period, the gate is driven high (pulled up) via a corresponding one of a plurality of different effective gate resistances. In response to a falling edge of the input signal, the integrated circuit causes the gate to be driven in a second sequence of time periods. In each period, the gate is driven low (pulled down) via a corresponding one of the different effective gate resistances. In one example, the duration of each time period is set by a corresponding external passive circuit component. The different effective gate resistances are set by external gate resistors disposed between the integrated circuit and the gate.

公开(公告)号：US20180062643A1

公开(公告)日：2018-03-01

申请号：US15245857

申请日：2016-08-24

申请人： Texas Instruments Incorporated

发明人： Olivier Trescases ,  Johan Tjeerd Strydom ,  Rajarshi Mukhopadhyay

IPC分类号： H03K17/687 ,  H03K5/08 ,  H01L29/16

CPC分类号： H03K17/687 ,  H01L29/1608 ,  H03K5/08 ,  H03K17/04206 ,  H03K17/0822

摘要： Methods and circuitry for driving a device through drive cycles wherein each drive cycle has a plurality of drive stages are disclosed. An example of the circuitry includes an output for coupling the circuitry to the device and a plurality of drive slices coupled in parallel to the output. Control circuitry selectively activates individual drive slices in the plurality of drive slices during each stage of a drive cycle.

公开(公告)号：US20180062642A1

公开(公告)日：2018-03-01

申请号：US15251692

申请日：2016-08-30

申请人： Infineon Technologies Austria AG

发明人： Wolfgang Frank ,  Remigiusz Viktor Boguszewicz

IPC分类号： H03K17/567 ,  H03K17/687

CPC分类号： H03K17/567 ,  H03K17/163 ,  H03K17/168 ,  H03K17/28 ,  H03K17/687 ,  H03K2217/0063 ,  H03K2217/0072

摘要： A circuit comprises an input terminal configured to receive an input signal. A high-side driver is configured to provide a high-side control signal to a high-side power transistor via a high-side terminal based on the input signal. A low-side driver is configured to provide a low-side control signal to a low-side power transistor based on the input signal. An interface is configured to couple the high-side terminal and the low-side terminal via a capacitor.

公开(公告)号：US09906220B1

公开(公告)日：2018-02-27

申请号：US15251692

申请日：2016-08-30

申请人： Infineon Technologies Austria AG

发明人： Wolfgang Frank ,  Remigiusz Viktor Boguszewicz

IPC分类号： H03K17/567 ,  H03K17/687

CPC分类号： H03K17/567 ,  H03K17/163 ,  H03K17/168 ,  H03K17/28 ,  H03K17/687 ,  H03K2217/0063 ,  H03K2217/0072

摘要： A circuit comprises an input terminal configured to receive an input signal. A high-side driver is configured to provide a high-side control signal to a high-side power transistor via a high-side terminal based on the input signal. A low-side driver is configured to provide a low-side control signal to a low-side power transistor based on the input signal. An interface is configured to couple the high-side terminal and the low-side terminal via a capacitor.