公开(公告)号：US20230300977A1

公开(公告)日：2023-09-21

申请号：US18009453

申请日：2021-06-11

Applicant: LG INNOTEK CO., LTD.

Inventor： Se Woong NA ,  Jung Eun HAN ,  Moo Seong KIM

IPC: H05K1/02 ,  H05K3/28

CPC classification number: H05K1/0298 ,  H05K3/28

Abstract: A circuit board according to an embodiment includes: an insulating layer including first to third regions; an outer layer circuit pattern disposed on an upper surface of the first to third regions of the insulating layer; and a solder resist including a first part disposed on the first region of the insulating layer, a second part disposed on the second region, and a third part disposed on the third region, wherein the outer layer circuit pattern includes: a first trace disposed on an upper surface of the first region of the insulating layer; and a second trace disposed on an upper surface of the third region of the insulating layer; wherein a height of the first trace is different from a height of the second trace; and an upper surface of the first part of the solder resist is positioned lower than an upper surface of the first trace.

公开(公告)号：US11765823B1

公开(公告)日：2023-09-19

申请号：US17825765

申请日：2022-05-26

Applicant: Signetik, LLC

Inventor： Steven Poulsen ,  Christopher Lawson ,  Nalini Muppala

IPC: H05K1/14 ,  H05K1/02 ,  H01R12/70 ,  H01R12/71 ,  H05K1/11

CPC classification number: H05K1/0298 ,  H01R12/7076 ,  H01R12/716 ,  H05K1/115 ,  H05K1/141 ,  H05K1/144 ,  H05K2201/10098 ,  H05K2201/10106 ,  H05K2201/10189

Abstract: A system-in-package cellular assembly is disclosed. The assembly may include a main board including a multi-layer printed circuit board. The main board may include one or more through holes and be detachably connectable to an end-product via the one or more through holes and one or more connecting members. The main board may be reversibly, electrically couplable to the end-product via the one or more through holes and the one or more connecting members. The assembly may include an add-on board including one or more through holes and be detachably connectable to the main board via one or more connectors. The add-on board may be reversibly, electrically couplable to the main board via one or more main board surface mount connectors and one or more add-on board surface mount connectors. The add-on board may include at least one of one or more sensors or one or more sensor through holes.

公开(公告)号：US20230292436A1

公开(公告)日：2023-09-14

申请号：US17689611

申请日：2022-03-08

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Melvin K. Benedict ,  Paul Danna ,  Chi Kim Sides ,  Wayne Vuong ,  Michael Chan

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K2201/09263 ,  H05K2201/09609

Abstract: One aspect of the instant application provides techniques to reduce the amount of crosstalk on single-ended signals in the pin field region of an integrated circuit device on a printed circuit board (PCB). The PCB can include a plurality of layers and an array of vias comprising a plurality of rows configured to route signals across layers. An inner layer of the PCB can include first and second signal traces positioned between first and second adjacent rows of the vias, the first signal trace positioned adjacent to the first row and the second signal trace positioned adjacent to the second row. The first signal trace can include at least one curved segment that curves around a substantial portion of a corresponding via in the first row such that separation between the first and second signal traces varies along the curved segment.

公开(公告)号：US11758655B2

公开(公告)日：2023-09-12

申请号：US17215916

申请日：2021-03-29

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Seung Eun Lee ,  Jae Woong Choi ,  Joo Hwan Jung ,  Yong Hoon Kim ,  Jin Won Lee

IPC: H05K1/11 ,  H05K1/18 ,  H05K1/02 ,  H05K1/03

CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/183 ,  H05K1/184 ,  H05K1/185 ,  H05K1/0366 ,  H05K1/181

Abstract: A printed circuit board includes a first insulating layer, a second insulating layer disposed on a lower surface of the first insulating layer, an electronic component embedded in the second insulating layer and at least partially in contact with the first insulating layer, a first wiring layer disposed on an upper surface of the first insulating layer, a second wiring layer disposed on a lower surface of the second insulating layer, and a first wiring via penetrating through the first and second insulating layers and connecting at least portions of the first and second wiring layers to each other.

公开(公告)号：US20230247763A1

公开(公告)日：2023-08-03

申请号：US18297857

申请日：2023-04-10

Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD. ,  SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.

Inventor： Koji NITTA ,  Yasushi MOCHIDA ,  Yoshio OKA ,  Shoichiro SAKAI ,  Tadahiro KAIBUKI ,  Junichi OKAUE

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/36 ,  H05K3/24

CPC classification number: H05K1/118 ,  H05K1/0265 ,  H05K1/0298 ,  H05K3/241 ,  H05K3/361 ,  H05K2201/094 ,  H05K2201/0338 ,  H05K2201/09236 ,  H05K2201/09736 ,  H05K2203/0723

Abstract: A flexible printed circuit board includes a base film having an insulating property and a plurality of interconnects laminated to at least one surface side of the base film. The plurality of interconnects includes a first interconnect and a second interconnect in a same plane. An average thickness of the second interconnect being greater than an average thickness of the first interconnect. A ratio of the average thickness of the second interconnect to the average thickness of the first interconnect is greater than or equal to 1.5 and less than or equal to 50. The first interconnect includes a first conductive underlayer and a first plating layer, and the second interconnect includes a second conductive underlayer, a second plating layer, and a third plating layer.

公开(公告)号：US20230225053A1

公开(公告)日：2023-07-13

申请号：US17647484

申请日：2022-01-10

Applicant: Quanta Computer Inc.

Inventor： Yaw-Tzorng Tsorng ,  Tung-Hsien Wu ,  Wei-Jie Chen

IPC: H05K1/14 ,  H05K1/02 ,  H01R12/71

CPC classification number: H05K1/141 ,  H05K1/0298 ,  H01R12/716

Abstract: A printed circuit board system includes a plurality of printed circuit board (PCB) assemblies that includes at least three PCB assemblies and a connecting module. The connecting module is coupled to each of the PCB assemblies. The connecting module is adapted to provide electrical and signal communications between each of the PCB assemblies. The connecting module is on different planes with respect to at least one of the PCB assemblies.

公开(公告)号：US11690172B2

公开(公告)日：2023-06-27

申请号：US17681279

申请日：2022-02-25

Applicant: Metrospec Technology, L.L.C.

Inventor： Henry V. Holec ,  Wm. Todd Crandell

IPC: H05K1/11 ,  H05K1/14 ,  H01R12/00 ,  H05K1/02 ,  H05K3/36 ,  H01R13/717 ,  H01R12/52 ,  H01R4/02 ,  F21Y107/30 ,  F21Y115/10 ,  H05K3/00

CPC classification number: H05K1/0293 ,  H01R4/02 ,  H01R12/00 ,  H01R12/523 ,  H01R13/717 ,  H05K1/0266 ,  H05K1/0269 ,  H05K1/0292 ,  H05K1/0298 ,  H05K1/11 ,  H05K1/113 ,  H05K1/118 ,  H05K1/14 ,  H05K1/144 ,  H05K3/363 ,  F21Y2107/30 ,  F21Y2115/10 ,  H05K1/147 ,  H05K3/0061 ,  H05K2201/041 ,  H05K2201/09481 ,  H05K2201/09918 ,  H05K2201/10106 ,  H05K2201/2027 ,  H05K2203/0228

Abstract: Embodiments of the invention include LED lighting systems and methods. For example, in some embodiments, an LED lighting system is included. The LED lighting system can include a flexible layered circuit structure that can include a top thermally conductive layer, a middle electrically insulating layer, a bottom thermally conductive layer, and a plurality of light emitting diodes mounted on the top layer. The LED lighting system can further include a housing substrate and a mounting structure. The mounting structure can be configured to suspend the layered circuit structure above the housing substrate with an air gap disposed in between the bottom thermally conductive layer of the flexible layered circuit structure and the housing substrate. The distance between the layered circuit structure and the support layer can be at least about 0.5 mm. Other embodiments are also included herein.

公开(公告)号：US20230199973A1

公开(公告)日：2023-06-22

申请号：US18169193

申请日：2023-02-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jiun-Yi Wu ,  Chien-Hsun Lee ,  Chen-Hua Yu ,  Chung-Shi Liu

IPC: H05K3/40 ,  H01L23/373 ,  H01L23/538 ,  H05K3/00 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K3/4046 ,  H01L23/3735 ,  H01L23/5384 ,  H05K3/0061 ,  H05K1/0298 ,  H05K1/113 ,  Y10T29/49165

Abstract: Circuit board includes conductive plate, core dielectric layer, metallization layer, first build-up stack, second build-up stack. Conductive plate has channels extending from top surface to bottom surface. Core dielectric layer extends on covering top surface and side surfaces of conductive plate. Metallization layer extends on core dielectric layer and within channels of conductive plate. Core dielectric layer insulates metallization layer from conductive plate. First build-up stack is disposed on top surface of conductive plate and includes conductive layers alternately stacked with dielectric layers. Conductive layers electrically connect to metallization layer. Second build-up stack is disposed on bottom surface of conductive plate. Second build-up stack includes bottommost dielectric layer and bottommost conductive layer. Bottommost dielectric layer covers bottom surface of conductive plate. Bottommost conductive layer is disposed on bottommost dielectric layer and electrically connects to metallization layer. First build-up stack includes more conductive and dielectric layers than second build-up stack.

公开(公告)号：US20230199959A1

公开(公告)日：2023-06-22

申请号：US17996285

申请日：2021-04-16

Applicant: LG INNOTEK CO., LTD.

Inventor： Won Suk JUNG

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K1/116 ,  H05K1/0298 ,  H05K2201/09854 ,  H05K2201/09827

Abstract: A circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on an upper surface of the first insulating layer; a first circuit pattern buried in a lower region of the first insulating layer and including a first via pad; a second circuit pattern disposed between the first insulating layer and the second insulating layer and including a second via pad; a third circuit pattern buried in an upper region of the second insulating layer and including a third via pad; a first via disposed in the first insulating layer and connecting the first via pad and the second via pad; and a second via disposed in the second insulating layer and connecting the second via pad and the third via pad, and wherein at least one of an upper surface and a lower surface of the second via includes a convex portion in an upward or downward direction.

公开(公告)号：US20230189451A1

公开(公告)日：2023-06-15

申请号：US17991627

申请日：2022-11-21

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Ki Hwan You ,  Seung Ju Lee ,  Tae Hun Kim ,  Chang Gon Kim ,  Yeon Ji Kim ,  Young Gon Kim ,  Ho Kwon Yoon ,  Eun Seok Kang

IPC: H05K3/46 ,  H01L21/768 ,  H05K1/02

CPC classification number: H05K3/4688 ,  H01L21/76805 ,  H05K1/0298

Abstract: A printed circuit board includes: a first insulating layer; a first circuit layer disposed on one surface of the first insulating layer and including a connection pad; a second insulating layer disposed on the one surface of the first insulating layer and embedding the first circuit layer; a via penetrating through the second insulating layer and connected to the first circuit layer; a metal post disposed on one surface of the second insulating layer and connected to the via; and a hole penetrating through the second insulating layer and exposing at least a portion of the connection pad of the first circuit layer. The metal post is spaced apart from the hole, and protrudes from the second insulating layer.